JP2020145407A - ワイヤボンディング連結構造を有する積層半導体パッケージ - Google Patents
ワイヤボンディング連結構造を有する積層半導体パッケージ Download PDFInfo
- Publication number
- JP2020145407A JP2020145407A JP2019217903A JP2019217903A JP2020145407A JP 2020145407 A JP2020145407 A JP 2020145407A JP 2019217903 A JP2019217903 A JP 2019217903A JP 2019217903 A JP2019217903 A JP 2019217903A JP 2020145407 A JP2020145407 A JP 2020145407A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- chip
- package
- hole
- semiconductor chips
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 355
- 239000000758 substrate Substances 0.000 claims abstract description 177
- 230000006870 function Effects 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 18
- 239000012790 adhesive layer Substances 0.000 description 9
- 230000010354 integration Effects 0.000 description 5
- 239000010410 layer Substances 0.000 description 5
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 238000004891 communication Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 101001045744 Sus scrofa Hepatocyte nuclear factor 1-beta Proteins 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/46—Structure, shape, material or disposition of the wire connectors prior to the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
- H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4845—Details of ball bonds
- H01L2224/48451—Shape
- H01L2224/48453—Shape of the interface with the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Geometry (AREA)
- Wire Bonding (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
5、6:半導体パッケージ構造物、
10、1010、2010:パッケージ基板、
110:ホールパターン、
110a、110b、1110b、2110b:第1および第2貫通ホール、
20a、20b、1020a、1020b、2020a、2020b:第1半導体チップ、
30a、30b、1030、2030:第2半導体チップ、
10S1、1010S1、2010S1:第1表面、
10S2、1010S2、2020S2:第2表面、
201A、201B、201C、201D:第1チップ接続パッド、
301A、301B、301C、301D:第2チップ接続パッド、
102A、102B、102C、102D、1102A、1102C:外部接続パッド、
120A、120B、120C、120D、1110b、2110b:外部接続手段、
210a、210b:第1チップパッド、
310a、310b:第2チップパッド、
510、520、5000:接着層、
710:導電性トレースパターン、
220a、220b:第1ボンディングワイヤ、
320a、320b:第2ボンディングワイヤ、
1301A、1301C、2301A、2301C:チップ接続パッド、
1310a、2310a:チップパッド、
1310、2410:接続パッド、
1320、2320、6000:ボンディングワイヤ。
Claims (21)
- 第1方向に延びる第1貫通ホールと、前記第1方向に垂直な第2方向に延びる第2貫通ホールとを備えるホールパターンを含むパッケージ基板と、
前記パッケージ基板の上部で前記第1貫通ホールと重なるように配置される第1半導体チップと、
前記パッケージ基板の上部で前記第2貫通ホールと重なるように配置される第2半導体チップと、
前記第1貫通ホールを介して前記第1半導体チップと前記パッケージ基板とを電気的に連結する第1ボンディングワイヤと、
前記第2貫通ホールを介して前記第2半導体チップと前記パッケージ基板とを電気的に連結する第2ボンディングワイヤとを含む、半導体パッケージ。 - 前記ホールパターンは、前記第1および第2貫通ホールが互いに交差する十字形態を有する、請求項1に記載の半導体パッケージ。
- 前記ホールパターンは、前記第1方向に沿って互いに離隔して配列される複数の第1貫通ホールと、前記第2方向に沿って互いに離隔して配列される複数の第2貫通ホールとを含む、請求項1に記載の半導体パッケージ。
- 前記複数の第1貫通ホールの間の第1空間、および前記複数の第2貫通ホールの間の第2空間の共通領域に配置され、
前記パッケージ基板内で配線層として機能する導電性トレースパターンをさらに含む、請求項3に記載の半導体パッケージ。 - 前記第1貫通ホールと重なる前記第1半導体チップの一領域に配置され、前記第1ボンディングワイヤと接合する第1チップパッドと、
前記第2貫通ホールと重なる前記第2半導体チップの一領域に配置され、前記第2ボンディングワイヤと接合する第2チップパッドとを含む、請求項1に記載の半導体パッケージ。 - 前記第1チップパッドは、前記第1半導体チップの中央領域に配置され、
前記第2チップパッドは、前記第2半導体チップの中央領域に配置される、請求項5に記載の半導体パッケージ。 - 前記第1半導体チップは、前記パッケージ基板上に配置され、
前記第2半導体チップは、前記第1半導体チップ上に配置される、請求項1に記載の半導体パッケージ。 - 一対の前記第1半導体チップが前記パッケージ基板の表面上で互いに平行に配置され、
一対の前記第2半導体チップが前記一対の第1半導体チップの上部で互いに平行に配置される、請求項1に記載の半導体パッケージ。 - 前記一対の第1半導体チップおよび前記一対の第2半導体チップは、互いに垂直方向に配置され、
前記パッケージ基板の表面上で4つの重畳領域を有するように配置される、請求項8に記載の半導体パッケージ。 - 前記第1および第2半導体チップは、すべて同一の大きさを有する、請求項1に記載の半導体パッケージ。
- 一対の前記第1半導体チップが前記パッケージ基板の表面上で互いに平行に配置され、
1つの前記第2半導体チップが前記一対の第1半導体チップの上部に配置され、
前記第2半導体チップは、前記一対の第1半導体チップの間に露出する前記第2貫通ホールと重なるように配置される、請求項1に記載の半導体パッケージ。 - 前記パッケージ基板は、
前記第1ボンディングワイヤと接続する第1チップ接続パッドと、
前記第2ボンディングワイヤと接続する第2チップ接続パッドとを備える、請求項1に記載の半導体パッケージ。 - 前記パッケージ基板は、
前記第1および第2チップ接続パッドが配置される表面と同一の表面に配置され、
前記第1および第2チップ接続パッドと電気的に連結される外部接続パッドを備える、請求項12に記載の半導体パッケージ。 - 互いに交差する第1貫通ホールおよび第2貫通ホールを備えるホールパターンを含むが、互いに対向する第1および第2表面上で前記ホールパターンによって定義される互いに異なる第1〜第4基板領域を有するパッケージ基板と、
前記第1表面の上部で、前記第1および第2基板領域、および前記第3および第4基板領域をそれぞれカバーするように配置され、前記第1貫通ホールと重なる一対の第1半導体チップと、
前記一対の第1半導体チップ上で、前記第1および第3基板領域、および前記第2および第4基板領域をそれぞれカバーするように配置され、前記第2貫通ホールと重なる一対の第2半導体チップと、
前記第1貫通ホールを介して前記一対の第1半導体チップと前記パッケージ基板とを電気的に連結する第1ボンディングワイヤと、
前記第2貫通ホールを介して前記一対の第2半導体チップと前記パッケージ基板とを電気的に連結する第2ボンディングワイヤとを含む、半導体パッケージ。 - 前記第1貫通ホールは、第1方向に延び、前記第2貫通ホールは、前記第1方向に垂直な第2方向に延びる、請求項14に記載の半導体パッケージ。
- 前記第1貫通ホールと重なる前記一対の第1半導体チップの一領域にそれぞれ配置され、前記第1ボンディングワイヤと接合する第1チップパッドと、
前記第2貫通ホールと重なる前記一対の第2半導体チップの一領域にそれぞれ配置され、前記第2ボンディングワイヤと接合する第2チップパッドとを含む、請求項14に記載の半導体パッケージ。 - 前記パッケージ基板は、
前記第2表面上に配置され、前記第1および第2ボンディングワイヤとそれぞれ接合する第1および第2チップ接続パッドを備える、請求項14に記載の半導体パッケージ。 - 前記パッケージ基板は、
前記第2表面上で、前記第1および第2チップ接続パッドと電気的に連結され、
外部接続手段が接続される外部接続パッドを備える、請求項14に記載の半導体パッケージ。 - 前記外部接続パッドは、前記第1〜第4基板領域にそれぞれ配置される、請求項18に記載の半導体パッケージ。
- 請求項1に記載の前記半導体パッケージが垂直方向に少なくとも2以上積層された構造物であり、
下層の前記半導体パッケージの第1および第2半導体チップが、上層の前記半導体パッケージのパッケージ基板と互いに対面するように配置され、
前記下層の前記半導体パッケージと前記上層の前記半導体パッケージとが接続手段によって電気的に連結される、半導体パッケージ構造物。 - 請求項1に記載の前記半導体パッケージが垂直方向に少なくとも2以上積層された構造物であり、
下層の前記半導体パッケージの第1および第2半導体チップが、上層の前記半導体パッケージの第1および第2半導体チップと互いに対面するように配置され、
前記下層の前記半導体パッケージと前記上層の前記半導体パッケージとが接続手段によって電気的に連結される、半導体パッケージ構造物。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020190024866A KR102647423B1 (ko) | 2019-03-04 | 2019-03-04 | 와이어 본딩 연결 구조를 가지는 반도체 패키지 및 이를 포함하는 반도체 패키지 구조물 |
KR10-2019-0024866 | 2019-03-04 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2020145407A true JP2020145407A (ja) | 2020-09-10 |
JP7474044B2 JP7474044B2 (ja) | 2024-04-24 |
Family
ID=72335622
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2019217903A Active JP7474044B2 (ja) | 2019-03-04 | 2019-12-02 | ワイヤボンディング連結構造を有する積層半導体パッケージ |
Country Status (4)
Country | Link |
---|---|
US (1) | US11322475B2 (ja) |
JP (1) | JP7474044B2 (ja) |
KR (1) | KR102647423B1 (ja) |
CN (1) | CN111653559B (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20220223560A1 (en) * | 2021-01-14 | 2022-07-14 | Changxin Memory Technologies, Inc. | Chip structure, packaging structure and manufacturing method of chip structure |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09275179A (ja) * | 1996-04-02 | 1997-10-21 | Hitachi Ltd | リードフレームおよびそれを用いた半導体集積回路装置ならびにその製造方法 |
JP2001223324A (ja) | 2000-02-10 | 2001-08-17 | Mitsubishi Electric Corp | 半導体装置 |
KR100460063B1 (ko) * | 2002-05-03 | 2004-12-04 | 주식회사 하이닉스반도체 | 센터 패드 칩 적층 볼 그리드 어레이 패키지 및 그 제조방법 |
JP2004063767A (ja) | 2002-07-29 | 2004-02-26 | Renesas Technology Corp | 半導体装置 |
KR100524975B1 (ko) | 2003-07-04 | 2005-10-31 | 삼성전자주식회사 | 반도체 장치의 적층형 패키지 |
JP3695458B2 (ja) * | 2003-09-30 | 2005-09-14 | セイコーエプソン株式会社 | 半導体装置、回路基板並びに電子機器 |
US7205656B2 (en) | 2005-02-22 | 2007-04-17 | Micron Technology, Inc. | Stacked device package for peripheral and center device pad layout device |
KR101163576B1 (ko) * | 2006-04-20 | 2012-07-06 | 엘지디스플레이 주식회사 | 유기 반도체물질을 이용한 액정표시장치용 어레이 기판 및그 제조 방법 |
JP2007324596A (ja) * | 2006-05-30 | 2007-12-13 | Samsung Electronics Co Ltd | コンタクトスペーサを有するコンタクト構造を具備した半導体素子及びその製造方法 |
KR20090009690A (ko) * | 2007-07-20 | 2009-01-23 | 엘지디스플레이 주식회사 | 인플레인 스위칭 모드의 액정표시장치 |
JP2009038142A (ja) | 2007-07-31 | 2009-02-19 | Elpida Memory Inc | 半導体積層パッケージ |
KR101465161B1 (ko) | 2008-09-04 | 2014-11-25 | 삼성전자주식회사 | 반도체 패키지 및 그 제조 방법 |
US8395191B2 (en) * | 2009-10-12 | 2013-03-12 | Monolithic 3D Inc. | Semiconductor device and structure |
US8338963B2 (en) | 2011-04-21 | 2012-12-25 | Tessera, Inc. | Multiple die face-down stacking for two or more die |
JP2012256629A (ja) * | 2011-06-07 | 2012-12-27 | Panasonic Corp | 半導体装置及びその製造方法 |
US8823165B2 (en) * | 2011-07-12 | 2014-09-02 | Invensas Corporation | Memory module in a package |
US9230609B2 (en) * | 2012-06-05 | 2016-01-05 | Rambus Inc. | Memory bandwidth aggregation using simultaneous access of stacked semiconductor memory die |
US9275786B2 (en) * | 2014-07-18 | 2016-03-01 | Qualcomm Incorporated | Superposed structure 3D orthogonal through substrate inductor |
KR20160141280A (ko) * | 2015-05-29 | 2016-12-08 | 에스케이하이닉스 주식회사 | 반도체 패키지 |
KR102639101B1 (ko) * | 2017-02-24 | 2024-02-22 | 에스케이하이닉스 주식회사 | 전자기간섭 차폐 구조를 갖는 반도체 패키지 |
-
2019
- 2019-03-04 KR KR1020190024866A patent/KR102647423B1/ko active IP Right Grant
- 2019-10-02 US US16/591,072 patent/US11322475B2/en active Active
- 2019-10-18 CN CN201910993150.XA patent/CN111653559B/zh active Active
- 2019-12-02 JP JP2019217903A patent/JP7474044B2/ja active Active
Also Published As
Publication number | Publication date |
---|---|
US11322475B2 (en) | 2022-05-03 |
CN111653559B (zh) | 2024-03-08 |
US20200286856A1 (en) | 2020-09-10 |
CN111653559A (zh) | 2020-09-11 |
KR20200106388A (ko) | 2020-09-14 |
KR102647423B1 (ko) | 2024-03-14 |
JP7474044B2 (ja) | 2024-04-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4751351B2 (ja) | 半導体装置とそれを用いた半導体モジュール | |
JP3495305B2 (ja) | 半導体装置及び半導体モジュール | |
JP2004095799A (ja) | 半導体装置およびその製造方法 | |
JP2014099591A (ja) | ブリッジング・ブロックを使用したマルチチップ・モジュール接続 | |
WO2004047173A1 (ja) | 半導体パッケージ及び積層型半導体パッケージ | |
US20200402959A1 (en) | Stacked semiconductor package having an interposer | |
US11682627B2 (en) | Semiconductor package including an interposer | |
KR20190119474A (ko) | 칩 스택 패키지 | |
JP2001177050A (ja) | 半導体装置 | |
JP4538830B2 (ja) | 半導体装置 | |
JP7474044B2 (ja) | ワイヤボンディング連結構造を有する積層半導体パッケージ | |
KR101486423B1 (ko) | 반도체 패키지 | |
KR20210096532A (ko) | 베이스 모듈에 복수의 칩들이 스택된 반도체 패키지 | |
JP4083376B2 (ja) | 半導体モジュール | |
JP3490601B2 (ja) | フィルムキャリアおよびそれを用いた積層型実装体 | |
US11444052B2 (en) | Semiconductor package including a package substrate including staggered bond fingers | |
TWI237355B (en) | Semiconductor device | |
US20210242176A1 (en) | Semiconductor packages | |
CN219286404U (zh) | 芯片互连结构 | |
TW202412202A (zh) | 半導體裝置及其製造方法 | |
JP2002368186A (ja) | 半導体装置 | |
JP4578220B2 (ja) | 半導体装置 | |
KR20230136426A (ko) | 차동 쌍 접속 패드 간 정렬된 와이어 배열을 가지는 반도체 패키지 | |
KR20130035802A (ko) | 반도체 패키지 및 그 제조 방법 | |
KR20070006459A (ko) | 칩 적층 패키지 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20221107 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20231024 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20231026 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20240109 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20240319 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20240412 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 7474044 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |