JP2020098820A - 半導体装置 - Google Patents
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Abstract
Description
以下、本実施の形態に関する半導体装置について説明する。
図1は、本実施の形態に関する、半導体装置の構成の例を概略的に示す平面図である。また、図2は、図1におけるA−A’断面における断面図である。
本実施の形態に関する半導体装置について説明する。なお、以下の説明においては、以上に記載された実施の形態で説明された構成要素と同様の構成要素については同じ符号を付して図示し、その詳細な説明については適宜省略するものとする。
図8は、本実施の形態に関する半導体装置の構成の例を概略的に示す断面図である。図8は、図1におけるA−A’断面における断面図に対応する。
次に、以上に記載された実施の形態によって生じる効果の例を示す。なお、以下の説明においては、以上に記載された実施の形態に例が示された具体的な構成に基づいて当該効果が記載されるが、同様の効果が生じる範囲で、本願明細書に例が示される他の具体的な構成と置き換えられてもよい。
以上に記載された実施の形態では、それぞれの構成要素の材質、材料、寸法、形状、相対的配置関係または実施の条件などについても記載する場合があるが、これらはすべての局面においてひとつの例であって、本願明細書に記載されたものに限られることはないものとする。
Claims (11)
- 第1の導電型の第1の半導体層と、
前記第1の半導体層の表層に形成される、第2の導電型の第2の半導体層と、
前記第2の半導体層の表層に形成される、第1の導電型の第3の半導体層と、
前記第1の半導体層の上面から、前記第2の半導体層および前記第3の半導体層を貫通して前記第1の半導体層の内部にまで達して形成される、少なくとも1つの第1のトレンチと、
前記第1のトレンチの内壁に形成されるゲート絶縁膜と、
前記第1のトレンチにおける前記ゲート絶縁膜の内側に形成されるゲート電極と、
前記ゲート電極を覆って形成される層間絶縁膜と、
前記層間絶縁膜から露出する前記第1の半導体層の上面から、前記第3の半導体層を貫通して前記第2の半導体層の内部にまで達して形成される、少なくとも1つの第2のトレンチと、
前記第2のトレンチの底部に接触して形成される、第2の導電型の第4の半導体層と、
前記層間絶縁膜および前記第2のトレンチを覆って形成される電極層とを備える、
半導体装置。 - 前記第4の半導体層の上面は、前記第2の半導体層の内部に位置する、
請求項1に記載の半導体装置。 - 前記第2のトレンチの底部が、前記第3の半導体層の下面よりも0.8μm以上深く位置する、
請求項1または請求項2に記載の半導体装置。 - 前記第2のトレンチの幅が、前記層間絶縁膜から露出する前記第1の半導体層の上面と前記電極層とが接触するコンタクトホールの幅よりも狭い、
請求項1から請求項3のうちのいずれか1項に記載の半導体装置。 - 前記第2のトレンチの幅は、50nm以上である、
請求項1から請求項4のうちのいずれか1項に記載の半導体装置。 - 前記第2の半導体層の下面に接触して形成される、第1の導電型の第5の半導体層をさらに備える、
請求項1から請求項5のうちのいずれか1項に記載の半導体装置。 - 複数の前記第1のトレンチと、
複数の前記第2のトレンチとを備え、
前記第1のトレンチの数が、前記第2のトレンチの数よりも多い、
請求項1から請求項6のうちのいずれか1項に記載の半導体装置。 - 2つの前記第1のトレンチに挟まれる領域であり、かつ、前記第2の半導体層と、前記第3の半導体層と、前記第4の半導体層と、前記第2のトレンチとが形成される領域を第1のセル領域とし、
2つの前記第1のトレンチに挟まれる領域であり、かつ、前記第1の半導体層の表層に形成される第2の導電型の第6の半導体層が形成される領域を第2のセル領域とし、
前記第1のセル領域と前記第2のセル領域とは、前記第1の半導体層の表層においてそれぞれ配列される、
請求項7に記載の半導体装置。 - 前記第1のセル領域と前記第2のセル領域とは、交互に配列される、
請求項8に記載の半導体装置。 - 2つの前記第1のトレンチに挟まれる領域であり、かつ、前記第2の半導体層と、前記第3の半導体層と、前記第4の半導体層と、前記第2のトレンチとが形成される領域を第1のセル領域とし、
2つの前記第1のトレンチに挟まれる領域であり、前記第2の半導体層と、前記第3の半導体層とが形成され、かつ、前記第4の半導体層と、前記第2のトレンチとが形成されない領域を第2のセル領域とし、
前記第1のセル領域と前記第2のセル領域とは、前記第1の半導体層の表層においてそれぞれ配列される、
請求項7に記載の半導体装置。 - 前記第1のセル領域は、前記第2のセル領域に対して2つおきに配列される、
請求項10に記載の半導体装置。
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JP2018235379A JP7085975B2 (ja) | 2018-12-17 | 2018-12-17 | 半導体装置 |
US16/592,614 US11004964B2 (en) | 2018-12-17 | 2019-10-03 | Semiconductor device |
DE102019219310.2A DE102019219310A1 (de) | 2018-12-17 | 2019-12-11 | Halbleitervorrichtung |
CN201911288616.2A CN111326510B (zh) | 2018-12-17 | 2019-12-12 | 半导体装置 |
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