JP2019532508A - 相関電子スイッチ構造及びその製造 - Google Patents
相関電子スイッチ構造及びその製造 Download PDFInfo
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- JP2019532508A JP2019532508A JP2019515507A JP2019515507A JP2019532508A JP 2019532508 A JP2019532508 A JP 2019532508A JP 2019515507 A JP2019515507 A JP 2019515507A JP 2019515507 A JP2019515507 A JP 2019515507A JP 2019532508 A JP2019532508 A JP 2019532508A
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Shaping switching materials
- H10N70/063—Shaping switching materials by etching of pre-deposited switching material layers, e.g. lithography
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/021—Formation of switching materials, e.g. deposition of layers
- H10N70/028—Formation of switching materials, e.g. deposition of layers by conversion of electrode material, e.g. oxidation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/823—Device geometry adapted for essentially horizontal current flow, e.g. bridge type devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
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- H10N70/881—Switching materials
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- H10N70/8833—Binary metal oxides, e.g. TaOx
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Abstract
Description
ρは端子402間に層を形成するために使用されたCEMの抵抗率であり;
Aはデバイスの断面積であり;そして、
l(エル)はデバイスの長さである。
2Ni2+→Ni1++Ni3+ ・・・(7)。
この場合、このような不均化は、式(7)に示すようなNi1++Ni3+としてのニッケルイオンの形成を指し、これは例えば、CEMデバイスの動作中に比較的高インピーダンス状態をもたらし得る。一実施形態では、カルボニル分子(CO)などの炭素含有配位子は、不均化反応及びその反転を可能にするように、CEMデバイスの動作中に電子の共有を可能にし得る:
Ni1++Ni3+→2Ni2+ ・・・(8)。
前述のように、式(8)に示す不均化反応の反転は、1つ又は複数の実施形態において、ニッケル系CEMが比較的低インピーダンス状態に戻ることを可能にし得る。
AX(気体)+BY(気体)=AB(固体)+XY(気体) ・・・(9)。
ここで、式(9)の「A」は、遷移金属、遷移金属酸化物、又はそれらの任意の組み合わせに対応する。一実施形態では、遷移金属酸化物はニッケルを含み得るが、例えばアルミニウム、カドミウム、クロム、コバルト、銅、金、鉄、マンガン、水銀、モリブデン、ニッケルパラジウム、レニウム、ルテニウム、銀、スズ、チタン、バナジウムなどの他の遷移金属及び/又は遷移金属酸化物も含み得る。
101、103 導電端子
102 材料、CEM
110 例示的な記号
210 可変レジスタ
220 可変キャパシタ
402、502、602、702、802、1102 端子
412 スイッチング領域を形成する層、真性部分
414 真性部分
422 導電領域を形成する層、p型ドープ部分
426 p型ドープ層
504、510 真性ノンドープCEMから形成された層
604 CEM部分
514、516 異なるドーパントで形成された層
704、804、1108、1205、1306 導電領域、導電部分
706、806、1106、1204、1304 (介在)スイッチング領域
708 ゲート端子
710 一対のゲート端子
712 3つ以上のゲート端子
812 少なくとも部分的に光透過性の電極
902、904、906、912 デバイス
1104 半導体デバイスの領域
1202、1212、1214 論理トランジスタ
1203、1206、1302 電極部分、電極
1204 CEMデバイス
1205 導電領域
1208、1210 1つ又は複数のCEM層
1308 基板
Claims (22)
- 第1の金属層の少なくとも一部分を露出させる第1のキャビティを形成するために基板の少なくとも一部分をエッチングするステップと、
前記キャビティを少なくとも部分的に充填するCEM構造を形成するために前記キャビティの上方に1つ又は複数のCEM層を形成するステップと、
を含む方法。 - 前記キャビティの上方に前記1つ又は複数のCEM層を形成するステップの前に、前記キャビティの上方に1つ又は複数の電極材料層を堆積させるステップをさらに含む、請求項1に記載の方法。
- 前記電極材料は、窒化チタン、白金、チタン、銅、アルミニウム、コバルト、ニッケル、タングステン、窒化タングステン、ケイ化コバルト、酸化ルテニウム、クロム、金、パラジウム、酸化インジウムスズ、タンタル、銀又はイリジウム、又はそれらの任意の組み合わせを含む、請求項2に記載の方法。
- 前記1つ又は複数のCEM層のうちの少なくとも1つの層は連続スイッチング領域を形成し、前記1つ又は複数の層のうちの少なくとも2つは少なくとも2つの導電領域を形成する、請求項1から3の何れか1項に記載の方法。
- 前記1つ又は複数のCEM層のうちの少なくとも1つの層は2つ以上の不連続スイッチング領域を形成し、前記1つ又は複数の層のうちの少なくとも2つは少なくとも2つの導電領域を形成する、請求項1から3の何れか1項に記載の方法。
- 前記2つ以上の不連続スイッチング領域は真性CEMを含み、前記2つ以上の導電領域はp型ドープCEMを含む、請求項5に記載の方法。
- 前記2つ以上の不連続スイッチング領域はp型ドープCEMを含み、前記2つ以上の導電領域は真性CEMを含む、請求項5に記載の方法。
- 前記CEM構造の上方に第2の金属層を形成するステップをさらに含む、請求項1から7の何れか1項に記載の方法。
- 前記CEM構造において第2のキャビティをエッチングするステップと、
前記第2のキャビティにおいて前記第2のキャビティを少なくとも部分的に充填する金属構造を形成するステップと、
をさらに含む、請求項1から8の何れか1項に記載の方法。 - 前記キャビティを少なくとも部分的に充填するCEM構造を形成するために前記キャビティの上方に1つ又は複数のCEM層を形成するステップは、前記キャビティの上方に前記1つ又は複数のCEM層を堆積させるステップをさらに含む、請求項1から9の何れか1項に記載の方法。
- 第1の金属層と、
前記第1の金属層上に形成された、前記第1の金属層の少なくとも一部分を露出させる第1のキャビティを含む基板と、
前記キャビティ内に形成された相関電子材料(CEM)構造であって、前記キャビティを少なくとも部分的に充填し、前記第1の金属層の少なくとも露出された部分上に形成された1つ又は複数のCEM層を含む、相関電子材料(CEM)構造と、
を含むデバイス。 - 前記CEM構造上に形成された第2の金属層をさらに含む、請求項11に記載のデバイス。
- 前記CEM構造内に形成された第2のキャビティ内に形成された金属構造をさらに含む、請求項11に記載のデバイス。
- 金属層の一部分をエッチングして前記金属層の残りの部分の間に不連続部を形成するステップと、
前記金属層の残りの部分及び前記不連続部の上方に1つ又は複数の相関電子材料(CEM)層を形成するステップと、
前記1つ又は複数のCEM層の上方において前記不連続部内に金属ビアを形成するステップと、
を含む方法。 - 前記1つ又は複数のCEM層を形成するステップの前に、前記金属層の残りの部分の上方に1つ又は複数の電極材料層を堆積させるステップをさらに含む、請求項14に記載の方法。
- 前記電極材料は窒化チタンを含む、請求項15に記載の方法。
- 前記金属層の残りの部分及び前記不連続部の上方に1つ又は複数の相関電子材料(CEM)層を形成するステップは、前記1つ又は複数の層を堆積させるステップをさらに含む、請求項14に記載の方法。
- 基板と、
前記基板上に形成された金属層であって、少なくとも1つの不連続部を含む、金属層と、
前記不連続部内に形成された1つ又は複数の相関電子材料(CEM)層と、
前記不連続部内に形成された金属ビアと、
を含むデバイス。 - 前記1つ又は複数のCEM層は、スイッチング領域を形成するための少なくとも1つ以上のCEM層と、2つ以上の導電領域を形成するための2つ以上のCEM層と、を含む、請求項18に記載のデバイス。
- 前記スイッチング領域は真性CEMを含み、前記2つ以上の導電領域はp型ドープCEMを含む、請求項19に記載のデバイス。
- 前記スイッチング領域はp型ドープCEMを含み、前記2つ以上の導電領域は真性CEMを含む、請求項19に記載のデバイス。
- 前記金属ビアと前記1つ又は複数のCEM層との間に形成された1つ又は複数の電極材料層をさらに含む、請求項18に記載のデバイス。
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