JP2019520636A - 高密度低バンド幅メモリと低密度高バンド幅メモリを組み合わせたメモリシステム - Google Patents
高密度低バンド幅メモリと低密度高バンド幅メモリを組み合わせたメモリシステム Download PDFInfo
- Publication number
- JP2019520636A JP2019520636A JP2018560772A JP2018560772A JP2019520636A JP 2019520636 A JP2019520636 A JP 2019520636A JP 2018560772 A JP2018560772 A JP 2018560772A JP 2018560772 A JP2018560772 A JP 2018560772A JP 2019520636 A JP2019520636 A JP 2019520636A
- Authority
- JP
- Japan
- Prior art keywords
- dram
- integrated circuit
- type
- memory
- drams
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015654 memory Effects 0.000 title claims abstract description 202
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 238000005265 energy consumption Methods 0.000 claims description 6
- 238000012536 packaging technology Methods 0.000 claims description 5
- 230000010354 integration Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 42
- 238000004806 packaging method and process Methods 0.000 description 20
- 238000013461 design Methods 0.000 description 16
- 239000000758 substrate Substances 0.000 description 12
- 241000724291 Tobacco streak virus Species 0.000 description 10
- 230000006870 function Effects 0.000 description 10
- 238000000034 method Methods 0.000 description 10
- 238000003860 storage Methods 0.000 description 10
- 238000003491 array Methods 0.000 description 8
- 238000012986 modification Methods 0.000 description 8
- 230000004048 modification Effects 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 6
- 230000003068 static effect Effects 0.000 description 6
- 239000003795 chemical substances by application Substances 0.000 description 4
- 230000009467 reduction Effects 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 230000004913 activation Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 238000012937 correction Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/402—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration individual to each memory cell, i.e. internal refresh
- G11C11/4023—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration individual to each memory cell, i.e. internal refresh using field effect transistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40607—Refresh operations in memory devices with an internal cache or data buffer
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/105—Aspects related to pads, pins or terminals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/108—Wide data ports
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Dram (AREA)
- Memory System (AREA)
- Semiconductor Memories (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
Description
以下の詳細な説明は、以下に簡単に記述する添付の図面を参照する。
以下の詳細な説明は、以下に簡単に記述する添付の図面を参照する。
Claims (29)
- 第1のタイプのダイナミックランダムアクセスメモリ(DRAM)を含む少なくとも1つの第1の集積回路と、
第2のタイプのDRAMを含む少なくとも1つの第2の集積回路であって、前記第2のタイプのDRAMは前記第1のタイプのDRAMよりも低密度であり、前記第2のタイプのDRAMへのアクセスはエネルギー消費が前記第1のタイプのDRAMへのアクセスよりも小さい、少なくとも1つの第2の集積回路と、
前記第2の集積回路と共にパッケージングされた第3の集積回路であって、前記第1の集積回路と前記第3の集積回路との間の接続と比較して、前記第3の集積回路と前記第2の集積との間の接続の長さ及びキャパシタンスを低減しており、前記メモリへのアクセスを制御するように構成されているメモリコントローラを含む第3の集積回路と、
を備えるシステム。 - 前記第2の集積回路は、前記第1のタイプのDRAM及び前記第2のタイプのDRAMを含み、前記メモリのために通信するように構成されている物理層回路を備える、請求項1に記載のシステム。
- 前記第1のタイプの複数のDRAMを含む複数の前記第1の集積回路を更に備える、請求項1に記載のシステム。
- 前記複数の第1の集積回路は、シリコン貫通電極(TSV)相互接続によりスタックにおいて接続されている、請求項3に記載のシステム。
- 前記複数の第1の集積回路の前記スタックは前記第2の集積回路に接続されており、前記TSV相互接続は前記第2の集積回路の物理層回路に接続されている、請求項3に記載のシステム。
- 前記第2のDRAMは前記物理層回路に接続されており、
前記物理層回路は、前記第3の集積回路への複数の前記第1のDRAMのための通信線、及び前記第3の集積回路への前記第2のDRAMのための通信線を含む、請求項5に記載のシステム。 - 前記第2の集積回路及び前記第3の集積回路は、チップオンウエハパッケージング技術を使用してパッケージングされている、請求項1に記載のシステム。
- 前記第2の集積回路及び前記第3の集積回路は、ウエハオンウエハパッケージング技術を使用してパッケージングされている、請求項1に記載のシステム。
- 前記第2の集積回路及び前記第3の集積回路は、チップオンチップパッケージング技術を使用してパッケージングされている、請求項1に記載のシステム。
- 前記第1の集積回路は、前記第2の集積回路及び前記第3の集積回路のパッケージ上に積層されている、請求項1に記載のシステム。
- 前記第1の集積回路は、前記第2の集積回路及び前記第3の集積回路を含む前記パッケージを用いたパッケージオンパッケージ構成でパッケージングされている、請求項10に記載のシステム。
- 前記第1の集積回路は、前記第1の集積回路及び前記第2の集積回路を含む前記パッケージの側面に配置されている、請求項1に記載のシステム。
- 前記第1の集積回路は複数の第1の集積回路のうちの1つであり、前記複数の第1の集積回路は、前記第2の集積回路及び前記第3の集積回路を含む前記パッケージの複数の側面に配置されている、請求項1に記載のシステム。
- 前記メモリコントローラは、複数のDRAM、前記第1のタイプのDRAMからのデータを、前記第2のタイプのDRAMの少なくとも1つの第2のDRAMにキャッシュするように構成されている、請求項1に記載のシステム。
- 前記第2のタイプのDRAMは、一ビット線当たりで前記第1のタイプのDRAMよりも少ないメモリセルを含む、請求項1に記載のシステム。
- 前記第2のタイプのDRAMは、一ワード線当たりで前記第1のタイプのDRAMよりも少ないメモリセルを含む、請求項1に記載のシステム。
- 前記第2のタイプのDRAMは、前記第1のタイプのDRAMよりも少ないバンクを含む、請求項1に記載のシステム。
- 前記第2のタイプのDRAMは、前記第1のタイプのDRAMよりも多くのバンクを含む、請求項1に記載のシステム。
- 前記第2のタイプのDRAMは、前記第1のタイプのDRAMよりも4倍〜16倍低密度である、請求項1に記載のシステム。
- 前記第2のタイプのDRAMは、前記第1のタイプのDRAMよりも6倍〜8倍低密度である、請求項19に記載のシステム。
- 前記第1のタイプのDRAMへの所定のアクセスは、前記第1の集積回路への第1のインタフェースを介した複数のコマンドを含み、
前記第2のタイプのDRAMへの所定のアクセスは、前記第2の集積回路への第2のインタフェースを介した単一のコマンドを含む、請求項1に記載のシステム。 - 少なくとも1つの第1の集積回路に第1のタイプのダイナミックランダムアクセスメモリ(DRAM)を含み、少なくとも1つの第2の集積回路に第2のタイプのDRAMを含むメモリであって、前記第1のタイプのDRAM及び前記第2のタイプのDRAMは少なくとも1つの特性が異なり、前記第2の集積回路は第1の物理層回路を含む、メモリと、
前記メモリに接続されており、メモリコントローラ及び第2の物理層回路を含む第3の集積回路と、
を備えるシステムであって、
前記第1の物理層回路は、前記第2の物理層回路に接続されており、前記第1の集積回路及び前記第2の集積回路の両方のために前記第2の物理層回路と通信するように構成されている、システム。 - 前記少なくとも1つの第1の集積回路はスタックにおける複数の集積回路であり、前記複数の集積回路は前記第1の物理層回路に接続されている、請求項22に記載のシステム。
- 前記複数の集積回路は、前記第1の物理層回路への相互接続の一部分を形成しているシリコン貫通電極を含む、請求項23に記載のシステム。
- 前記メモリコントローラは、前記第1のタイプのDRAMのためのキャッシュとして前記第2のタイプのDRAMを動作させるように構成されている、請求項22に記載のシステム。
- 前記第2のタイプのDRAMは前記第1のタイプのDRAMよりも高いバンド幅を有する、請求項22に記載のシステム。
- 前記第2のタイプのDRAMは前記第1のタイプのDRAMよりも低いレイテンシを有する、請求項22に記載のシステム。
- 前記第1のタイプのDRAMは前記第2のタイプのDRAMよりも密度が高い、請求項22に記載のシステム。
- 第1のタイプの第1のダイナミックランダムアクセスメモリ(DRAM)を含む1つ以上の第1の集積回路と、
スタックにおいて前記1つ以上の第1の集積回路に接続された第2の集積回路であって、第2のDRAMタイプの第2のDRAMを含み、前記第1のDRAM及び前記第2のDRAMのために通信するように構成されている物理層回路を更に含む第2の集積回路と、
を備えるメモリ。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2021034975A JP7169387B2 (ja) | 2016-06-27 | 2021-03-05 | 高密度低バンド幅メモリと低密度高バンド幅メモリを組み合わせたメモリシステム |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201662355012P | 2016-06-27 | 2016-06-27 | |
US62/355,012 | 2016-06-27 | ||
PCT/US2017/020976 WO2018004756A1 (en) | 2016-06-27 | 2017-03-06 | Memory system having combined high density, low bandwidth and low density, high bandwidth memories |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2021034975A Division JP7169387B2 (ja) | 2016-06-27 | 2021-03-05 | 高密度低バンド幅メモリと低密度高バンド幅メモリを組み合わせたメモリシステム |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2019520636A true JP2019520636A (ja) | 2019-07-18 |
Family
ID=60787628
Family Applications (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2018560772A Pending JP2019520636A (ja) | 2016-06-27 | 2017-03-06 | 高密度低バンド幅メモリと低密度高バンド幅メモリを組み合わせたメモリシステム |
JP2021034975A Active JP7169387B2 (ja) | 2016-06-27 | 2021-03-05 | 高密度低バンド幅メモリと低密度高バンド幅メモリを組み合わせたメモリシステム |
JP2022172887A Active JP7402959B2 (ja) | 2016-06-27 | 2022-10-28 | 高密度低バンド幅メモリと低密度高バンド幅メモリを組み合わせたメモリシステム |
JP2023208341A Active JP7451819B2 (ja) | 2016-06-27 | 2023-12-11 | 高密度低バンド幅メモリと低密度高バンド幅メモリを組み合わせたメモリシステム |
Family Applications After (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2021034975A Active JP7169387B2 (ja) | 2016-06-27 | 2021-03-05 | 高密度低バンド幅メモリと低密度高バンド幅メモリを組み合わせたメモリシステム |
JP2022172887A Active JP7402959B2 (ja) | 2016-06-27 | 2022-10-28 | 高密度低バンド幅メモリと低密度高バンド幅メモリを組み合わせたメモリシステム |
JP2023208341A Active JP7451819B2 (ja) | 2016-06-27 | 2023-12-11 | 高密度低バンド幅メモリと低密度高バンド幅メモリを組み合わせたメモリシステム |
Country Status (6)
Country | Link |
---|---|
US (5) | US10573368B2 (ja) |
EP (3) | EP3852107A1 (ja) |
JP (4) | JP2019520636A (ja) |
KR (4) | KR102273002B1 (ja) |
CN (2) | CN111210857B (ja) |
WO (1) | WO2018004756A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2023209491A1 (ja) * | 2022-04-29 | 2023-11-02 | 株式会社半導体エネルギー研究所 | 半導体装置 |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102273002B1 (ko) | 2016-06-27 | 2021-07-06 | 애플 인크. | 조합된 높은 밀도, 낮은 대역폭 및 낮은 밀도, 높은 대역폭 메모리들을 갖는 메모리 시스템 |
US10607136B2 (en) * | 2017-08-03 | 2020-03-31 | Xcelsis Corporation | Time borrowing between layers of a three dimensional chip stack |
US10672745B2 (en) | 2016-10-07 | 2020-06-02 | Xcelsis Corporation | 3D processor |
US10580735B2 (en) | 2016-10-07 | 2020-03-03 | Xcelsis Corporation | Stacked IC structure with system level wiring on multiple sides of the IC die |
US10580757B2 (en) | 2016-10-07 | 2020-03-03 | Xcelsis Corporation | Face-to-face mounted IC dies with orthogonal top interconnect layers |
KR102512017B1 (ko) | 2016-10-07 | 2023-03-17 | 엑셀시스 코포레이션 | 직접-접합된 네이티브 상호접속부 및 능동 베이스 다이 |
US10672663B2 (en) | 2016-10-07 | 2020-06-02 | Xcelsis Corporation | 3D chip sharing power circuit |
KR20190105346A (ko) * | 2018-03-05 | 2019-09-17 | 삼성전자주식회사 | 메모리 패키지 및 메모리 장치 |
US11581282B2 (en) * | 2018-08-30 | 2023-02-14 | Intel Corporation | Serializer-deserializer die for high speed signal interconnect |
US11171115B2 (en) | 2019-03-18 | 2021-11-09 | Kepler Computing Inc. | Artificial intelligence processor with three-dimensional stacked memory |
US11836102B1 (en) | 2019-03-20 | 2023-12-05 | Kepler Computing Inc. | Low latency and high bandwidth artificial intelligence processor |
KR20200138493A (ko) | 2019-05-30 | 2020-12-10 | 삼성전자주식회사 | 반도체 패키지 |
US11152343B1 (en) | 2019-05-31 | 2021-10-19 | Kepler Computing, Inc. | 3D integrated ultra high-bandwidth multi-stacked memory |
US11844223B1 (en) | 2019-05-31 | 2023-12-12 | Kepler Computing Inc. | Ferroelectric memory chiplet as unified memory in a multi-dimensional packaging |
DE112019007422T5 (de) * | 2019-05-31 | 2022-02-24 | Micron Technology, Inc. | Speicherkomponente für ein system-on-chip-gerät |
KR20220013735A (ko) | 2020-07-27 | 2022-02-04 | 삼성전자주식회사 | 인터포저를 구비하는 반도체 패키지 |
US11360695B2 (en) * | 2020-09-16 | 2022-06-14 | Micron Technology, Inc. | Apparatus with combinational access mechanism and methods for operating the same |
US20220188606A1 (en) * | 2020-12-14 | 2022-06-16 | Micron Technology, Inc. | Memory Configuration to Support Deep Learning Accelerator in an Integrated Circuit Device |
US11789641B2 (en) * | 2021-06-16 | 2023-10-17 | Intel Corporation | Three dimensional circuit systems and methods having memory hierarchies |
US11791233B1 (en) | 2021-08-06 | 2023-10-17 | Kepler Computing Inc. | Ferroelectric or paraelectric memory and logic chiplet with thermal management in a multi-dimensional packaging |
TWI769094B (zh) * | 2021-10-07 | 2022-06-21 | 瑞昱半導體股份有限公司 | 多晶粒封裝 |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003282823A (ja) * | 2002-03-26 | 2003-10-03 | Toshiba Corp | 半導体集積回路 |
US20090182977A1 (en) * | 2008-01-16 | 2009-07-16 | S. Aqua Semiconductor Llc | Cascaded memory arrangement |
US20140164713A1 (en) * | 2012-12-09 | 2014-06-12 | Advanced Micro Devices | Bypassing Memory Requests to a Main Memory |
US20140215177A1 (en) * | 2012-08-02 | 2014-07-31 | Boo Jin Kim | Methods and Systems for Managing Heterogeneous Memories |
US20150006805A1 (en) * | 2013-06-28 | 2015-01-01 | Dannie G. Feekes | Hybrid multi-level memory architecture |
US20150113356A1 (en) * | 2013-10-23 | 2015-04-23 | Etron Technology, Inc. | System-in-package module with memory |
JP2015079511A (ja) * | 2013-10-16 | 2015-04-23 | 三星電子株式会社Samsung Electronics Co.,Ltd. | システムとモバイルコンピューティング装置 |
JP2015528599A (ja) * | 2012-08-06 | 2015-09-28 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドAdvanced Micro Devices Incorporated | メタデータ管理による積層メモリデバイス |
Family Cites Families (41)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5877780A (en) | 1996-08-08 | 1999-03-02 | Lu; Hsuehchung Shelton | Semiconductor chip having multiple independent memory sections, at least one of which includes simultaneously accessible arrays |
JP3092557B2 (ja) * | 1997-09-16 | 2000-09-25 | 日本電気株式会社 | 半導体記憶装置 |
TW498212B (en) | 2000-08-12 | 2002-08-11 | Acer Labs Inc | Computer system to support DRAM of different types |
US20030002692A1 (en) | 2001-05-31 | 2003-01-02 | Mckitrick Mark A. | Point sound masking system offering visual privacy |
US7145819B2 (en) * | 2001-06-11 | 2006-12-05 | Analog Devices, Inc. | Method and apparatus for integrated circuit with DRAM |
KR100396894B1 (ko) * | 2001-06-27 | 2003-09-02 | 삼성전자주식회사 | 버스 효율을 향상시키는 메모리 시스템 및 반도체 메모리장치와 상기 반도체 메모리 장치의 리프레쉬 방법 |
KR100393232B1 (ko) * | 2001-10-23 | 2003-07-31 | 삼성전자주식회사 | 제1 또는 제2메모리 아키텍쳐로의 구현이 가능한 반도체메모리 장치 및 이를 이용한 메모리 시스템 |
CN1421861A (zh) * | 2001-11-26 | 2003-06-04 | 萧正杰 | 高性能半导体存储设备 |
US6807106B2 (en) | 2001-12-14 | 2004-10-19 | Sandisk Corporation | Hybrid density memory card |
US20030158995A1 (en) * | 2002-02-15 | 2003-08-21 | Ming-Hsien Lee | Method for DRAM control with adjustable page size |
US7110306B2 (en) * | 2004-06-28 | 2006-09-19 | United Memories, Inc. | Dual access DRAM |
US7385858B2 (en) * | 2005-11-30 | 2008-06-10 | Mosaid Technologies Incorporated | Semiconductor integrated circuit having low power consumption with self-refresh |
US7486104B2 (en) * | 2006-06-02 | 2009-02-03 | Rambus Inc. | Integrated circuit with graduated on-die termination |
DE102006049867B4 (de) | 2006-10-23 | 2021-09-16 | Siemens Aktiengesellschaft | Werkzeugmaschine und Verfahren zur Unterdrückung von Ratterschwingungen |
US9195602B2 (en) * | 2007-03-30 | 2015-11-24 | Rambus Inc. | System including hierarchical memory modules having different types of integrated circuit memory devices |
US7822911B2 (en) * | 2007-08-15 | 2010-10-26 | Micron Technology, Inc. | Memory device and method with on-board cache system for facilitating interface with multiple processors, and computer system using same |
TW200917277A (en) | 2007-10-15 | 2009-04-16 | A Data Technology Co Ltd | Adaptive hybrid density memory storage device and control method thereof |
JP5127435B2 (ja) * | 2007-11-01 | 2013-01-23 | パナソニック株式会社 | 半導体記憶装置 |
US7973310B2 (en) * | 2008-07-11 | 2011-07-05 | Chipmos Technologies Inc. | Semiconductor package structure and method for manufacturing the same |
KR20100010167A (ko) | 2008-07-22 | 2010-02-01 | 현대자동차주식회사 | 차량의 스티프너 마운팅 구조 |
US8097956B2 (en) | 2009-03-12 | 2012-01-17 | Apple Inc. | Flexible packaging for chip-on-chip and package-on-package technologies |
JP5389490B2 (ja) | 2009-03-23 | 2014-01-15 | 東京エレクトロン株式会社 | 三次元集積回路の製造方法及び装置 |
US8219746B2 (en) | 2009-10-08 | 2012-07-10 | International Business Machines Corporation | Memory package utilizing at least two types of memories |
US8612809B2 (en) | 2009-12-31 | 2013-12-17 | Intel Corporation | Systems, methods, and apparatuses for stacked memory |
US8595429B2 (en) | 2010-08-24 | 2013-11-26 | Qualcomm Incorporated | Wide input/output memory with low density, low latency and high density, high latency blocks |
KR20130141635A (ko) | 2010-12-15 | 2013-12-26 | 알리손 트랜스미션, 인크. | 토로이달 트랙션 드라이브 변속기용 배리에이터 스위칭 밸브 구조물 |
JP2012209424A (ja) | 2011-03-30 | 2012-10-25 | Tokyo Electron Ltd | 半導体装置の製造方法 |
US9432298B1 (en) * | 2011-12-09 | 2016-08-30 | P4tents1, LLC | System, method, and computer program product for improving memory systems |
US20130031327A1 (en) * | 2011-07-28 | 2013-01-31 | Yung Chang | System and method for allocating cache memory |
US8957691B2 (en) | 2011-10-21 | 2015-02-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Probe cards for probing integrated circuits |
US9753858B2 (en) * | 2011-11-30 | 2017-09-05 | Advanced Micro Devices, Inc. | DRAM cache with tags and data jointly stored in physical rows |
KR101867571B1 (ko) | 2012-07-03 | 2018-06-15 | 현대자동차주식회사 | 차량용 도어스위치 |
US8526234B1 (en) | 2012-11-16 | 2013-09-03 | Avalanche Technology, Inc. | Controller management of memory array of storage device using magnetic random access memory (MRAM) |
KR20140070301A (ko) * | 2012-11-29 | 2014-06-10 | 삼성전자주식회사 | 다이나믹 랜덤 억세스 메모리에 캐시 기능이 탑재된 반도체 메모리 장치 |
US20140146589A1 (en) * | 2012-11-29 | 2014-05-29 | Samsung Electronics Co., Ltd. | Semiconductor memory device with cache function in dram |
US9053039B2 (en) * | 2012-12-21 | 2015-06-09 | Advanced Micro Devices, Inc. | Installation cache |
US9110592B2 (en) * | 2013-02-04 | 2015-08-18 | Microsoft Technology Licensing, Llc | Dynamic allocation of heterogenous memory in a computing system |
US9679615B2 (en) * | 2013-03-15 | 2017-06-13 | Micron Technology, Inc. | Flexible memory system with a controller and a stack of memory |
KR102238717B1 (ko) | 2014-10-27 | 2021-04-09 | 삼성전자주식회사 | 메모리 시스템 및 이의 동작 방법 |
KR102273002B1 (ko) | 2016-06-27 | 2021-07-06 | 애플 인크. | 조합된 높은 밀도, 낮은 대역폭 및 낮은 밀도, 높은 대역폭 메모리들을 갖는 메모리 시스템 |
US10818331B2 (en) * | 2016-09-27 | 2020-10-27 | Spin Memory, Inc. | Multi-chip module for MRAM devices with levels of dynamic redundancy registers |
-
2017
- 2017-03-06 KR KR1020187034289A patent/KR102273002B1/ko active IP Right Grant
- 2017-03-06 KR KR1020237035718A patent/KR20230151553A/ko not_active Application Discontinuation
- 2017-03-06 EP EP21162067.9A patent/EP3852107A1/en active Pending
- 2017-03-06 CN CN202010007966.3A patent/CN111210857B/zh active Active
- 2017-03-06 EP EP22203895.2A patent/EP4145447A1/en active Pending
- 2017-03-06 US US16/098,916 patent/US10573368B2/en active Active
- 2017-03-06 KR KR1020217020299A patent/KR102392083B1/ko active IP Right Grant
- 2017-03-06 JP JP2018560772A patent/JP2019520636A/ja active Pending
- 2017-03-06 CN CN201780033666.9A patent/CN109219848B/zh active Active
- 2017-03-06 KR KR1020227013909A patent/KR102592777B1/ko active IP Right Grant
- 2017-03-06 WO PCT/US2017/020976 patent/WO2018004756A1/en active Search and Examination
- 2017-03-06 EP EP17820683.5A patent/EP3449482A4/en not_active Withdrawn
-
2020
- 2020-01-06 US US16/734,595 patent/US10916290B2/en active Active
-
2021
- 2021-01-04 US US17/140,753 patent/US11468935B2/en active Active
- 2021-03-05 JP JP2021034975A patent/JP7169387B2/ja active Active
-
2022
- 2022-08-25 US US17/895,433 patent/US11830534B2/en active Active
- 2022-10-28 JP JP2022172887A patent/JP7402959B2/ja active Active
-
2023
- 2023-11-21 US US18/515,649 patent/US20240161804A1/en active Pending
- 2023-12-11 JP JP2023208341A patent/JP7451819B2/ja active Active
Patent Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003282823A (ja) * | 2002-03-26 | 2003-10-03 | Toshiba Corp | 半導体集積回路 |
US20090182977A1 (en) * | 2008-01-16 | 2009-07-16 | S. Aqua Semiconductor Llc | Cascaded memory arrangement |
WO2009092036A1 (en) * | 2008-01-16 | 2009-07-23 | S. Aqua Semiconductor Llc | Cascaded memory arrangement |
JP2011510408A (ja) * | 2008-01-16 | 2011-03-31 | エス. アクア セミコンダクター, エルエルシー | 従属接続メモリ配置 |
US20140215177A1 (en) * | 2012-08-02 | 2014-07-31 | Boo Jin Kim | Methods and Systems for Managing Heterogeneous Memories |
JP2015528599A (ja) * | 2012-08-06 | 2015-09-28 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドAdvanced Micro Devices Incorporated | メタデータ管理による積層メモリデバイス |
US20140164713A1 (en) * | 2012-12-09 | 2014-06-12 | Advanced Micro Devices | Bypassing Memory Requests to a Main Memory |
US20150006805A1 (en) * | 2013-06-28 | 2015-01-01 | Dannie G. Feekes | Hybrid multi-level memory architecture |
JP2015079511A (ja) * | 2013-10-16 | 2015-04-23 | 三星電子株式会社Samsung Electronics Co.,Ltd. | システムとモバイルコンピューティング装置 |
KR20150044370A (ko) * | 2013-10-16 | 2015-04-24 | 삼성전자주식회사 | 이종 메모리들을 관리하는 시스템들 |
US20150113356A1 (en) * | 2013-10-23 | 2015-04-23 | Etron Technology, Inc. | System-in-package module with memory |
CN104575584A (zh) * | 2013-10-23 | 2015-04-29 | 钰创科技股份有限公司 | 具有嵌入式内存的系统级封装内存模块 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2023209491A1 (ja) * | 2022-04-29 | 2023-11-02 | 株式会社半導体エネルギー研究所 | 半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
JP7451819B2 (ja) | 2024-03-18 |
KR20230151553A (ko) | 2023-11-01 |
JP7169387B2 (ja) | 2022-11-10 |
EP3449482A4 (en) | 2019-12-11 |
CN109219848B (zh) | 2020-01-03 |
JP2021099850A (ja) | 2021-07-01 |
US10573368B2 (en) | 2020-02-25 |
KR102592777B1 (ko) | 2023-10-25 |
US20190198083A1 (en) | 2019-06-27 |
EP3449482A1 (en) | 2019-03-06 |
US20240161804A1 (en) | 2024-05-16 |
EP4145447A1 (en) | 2023-03-08 |
CN111210857B (zh) | 2023-07-18 |
JP2024028937A (ja) | 2024-03-05 |
US11830534B2 (en) | 2023-11-28 |
EP3852107A1 (en) | 2021-07-21 |
JP7402959B2 (ja) | 2023-12-21 |
KR20180133524A (ko) | 2018-12-14 |
WO2018004756A1 (en) | 2018-01-04 |
KR102392083B1 (ko) | 2022-04-29 |
KR20220058966A (ko) | 2022-05-10 |
US10916290B2 (en) | 2021-02-09 |
US20210125657A1 (en) | 2021-04-29 |
US20200143866A1 (en) | 2020-05-07 |
KR102273002B1 (ko) | 2021-07-06 |
JP2023017848A (ja) | 2023-02-07 |
CN111210857A (zh) | 2020-05-29 |
US20220415379A1 (en) | 2022-12-29 |
US11468935B2 (en) | 2022-10-11 |
KR20210083406A (ko) | 2021-07-06 |
CN109219848A (zh) | 2019-01-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP7451819B2 (ja) | 高密度低バンド幅メモリと低密度高バンド幅メモリを組み合わせたメモリシステム | |
TWI585775B (zh) | 記憶裝置 | |
US9851401B2 (en) | Stacked memory device and semiconductor memory system including the same | |
JP5559507B2 (ja) | 半導体装置及びこれを備える情報処理システム | |
US20100078635A1 (en) | Semiconductor device | |
JP2009522782A (ja) | 構成可能な入力と出力を有するメモリスタッキングシステムと方法 | |
TW202145492A (zh) | 包括堆疊在控制器晶粒上方的核心晶粒的堆疊封裝件 | |
US11289174B2 (en) | Stacked semiconductor device and semiconductor system including the same | |
US8611127B1 (en) | Stacked memory device having a scalable bandwidth interface | |
US11164608B2 (en) | Centralized placement of command and address in memory devices | |
JP2024069323A (ja) | 高密度低バンド幅メモリと低密度高バンド幅メモリを組み合わせたメモリシステム | |
CN114610665A (zh) | 存储器扩展卡 | |
CN117389459A (zh) | 存储器、芯片堆叠结构、芯片封装结构及电子设备 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20181119 Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20181217 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20181119 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20191128 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20191223 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20200323 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20200522 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20201105 |