JP2019186330A5 - - Google Patents

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Publication number
JP2019186330A5
JP2019186330A5 JP2018073456A JP2018073456A JP2019186330A5 JP 2019186330 A5 JP2019186330 A5 JP 2019186330A5 JP 2018073456 A JP2018073456 A JP 2018073456A JP 2018073456 A JP2018073456 A JP 2018073456A JP 2019186330 A5 JP2019186330 A5 JP 2019186330A5
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JP
Japan
Prior art keywords
metal layer
layer
pad
opening
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2018073456A
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English (en)
Japanese (ja)
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JP2019186330A (ja
JP7112873B2 (ja
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Priority to JP2018073456A priority Critical patent/JP7112873B2/ja
Priority claimed from JP2018073456A external-priority patent/JP7112873B2/ja
Priority to US16/373,951 priority patent/US10886211B2/en
Publication of JP2019186330A publication Critical patent/JP2019186330A/ja
Publication of JP2019186330A5 publication Critical patent/JP2019186330A5/ja
Application granted granted Critical
Publication of JP7112873B2 publication Critical patent/JP7112873B2/ja
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JP2018073456A 2018-04-05 2018-04-05 配線基板、半導体パッケージ及び配線基板の製造方法 Active JP7112873B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2018073456A JP7112873B2 (ja) 2018-04-05 2018-04-05 配線基板、半導体パッケージ及び配線基板の製造方法
US16/373,951 US10886211B2 (en) 2018-04-05 2019-04-03 Wiring board and semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2018073456A JP7112873B2 (ja) 2018-04-05 2018-04-05 配線基板、半導体パッケージ及び配線基板の製造方法

Publications (3)

Publication Number Publication Date
JP2019186330A JP2019186330A (ja) 2019-10-24
JP2019186330A5 true JP2019186330A5 (enExample) 2021-02-12
JP7112873B2 JP7112873B2 (ja) 2022-08-04

Family

ID=68097357

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018073456A Active JP7112873B2 (ja) 2018-04-05 2018-04-05 配線基板、半導体パッケージ及び配線基板の製造方法

Country Status (2)

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US (1) US10886211B2 (enExample)
JP (1) JP7112873B2 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7459492B2 (ja) * 2019-11-29 2024-04-02 大日本印刷株式会社 配線基板
KR20220097718A (ko) * 2020-12-31 2022-07-08 삼성전자주식회사 배선 기판 및 이를 포함하는 반도체 모듈

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6350386B1 (en) * 2000-09-20 2002-02-26 Charles W. C. Lin Method of making a support circuit with a tapered through-hole for a semiconductor chip assembly
US8338287B2 (en) * 2010-03-24 2012-12-25 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
US8389397B2 (en) * 2010-09-14 2013-03-05 Taiwan Semiconductor Manufacturing Company, Ltd. Method for reducing UBM undercut in metal bump structures
JP2013093405A (ja) 2011-10-25 2013-05-16 Ngk Spark Plug Co Ltd 配線基板及びその製造方法
JP6057681B2 (ja) 2012-11-21 2017-01-11 新光電気工業株式会社 配線基板及びその製造方法
JP6298722B2 (ja) 2014-06-10 2018-03-20 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
JP2016035969A (ja) 2014-08-01 2016-03-17 味の素株式会社 回路基板及びその製造方法
JP6780933B2 (ja) 2015-12-18 2020-11-04 新光電気工業株式会社 端子構造、端子構造の製造方法、及び配線基板

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