JP2019125722A - 貼り合わせウェーハの製造方法、貼り合わせウェーハ - Google Patents
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- 238000000034 method Methods 0.000 title abstract description 13
- 238000005498 polishing Methods 0.000 claims abstract description 80
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 62
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 239000004744 fabric Substances 0.000 claims abstract description 21
- 238000000151 deposition Methods 0.000 claims description 5
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- 230000007547 defect Effects 0.000 abstract description 14
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- 235000012431 wafers Nutrition 0.000 description 85
- 238000005259 measurement Methods 0.000 description 9
- 230000000052 comparative effect Effects 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000005033 Fourier transform infrared spectroscopy Methods 0.000 description 2
- 238000004566 IR spectroscopy Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 239000008119 colloidal silica Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000011156 evaluation Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- -1 hydrogen ions Chemical class 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
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Abstract
Description
本発明の貼り合わせウェーハの製造方法は、支持基板用ウェーハと、活性層用ウェーハとを、絶縁膜を介して貼り合わせて、貼り合わせウェーハを製造する方法であって、
前記支持基板用ウェーハの貼り合わせ面側に、多結晶シリコン層を堆積する、多結晶シリコン堆積工程と、
研磨布を用いて前記多結晶シリコン層の表面を研磨する、多結晶シリコン層研磨工程と、
前記支持基板用ウェーハ及び前記活性層用ウェーハの少なくともいずれかの貼り合わせ面に、前記絶縁膜を形成する、絶縁膜形成工程と、
前記絶縁膜を介して、前記支持基板用ウェーハの前記多結晶シリコン層の研磨面と、前記活性層用ウェーハとを、貼り合わせる、貼り合わせ工程と、を含み、
前記研磨布の沈み込み量を、
沈み込み量(μm)=研磨布の厚さ(μm)×圧縮率(%/(N/cm2))×荷重(N/cm2)で定義するとき、
前記研磨布の沈み込み量は、50〜90μmであり、且つ、前記研磨布の表面硬度(ASKER C)は、50〜60であることを特徴とする。
前記多結晶シリコンウェーハ層は、厚さのばらつきΔtが5%以下であり、
前記多結晶シリコンウェーハ層を研磨した後の、前記支持基板用ウェーハは、GBIRが0.2μm以下、SFQRが0.06μm以下であることを特徴とする。
Δt={(最大厚さ−最小厚さ)/(最大厚さ+最小厚さ)}*100(%)
図1は、本発明の一実施形態にかかる貼り合わせウェーハの製造方法のフロー図である。図2は、本発明の一実施形態にかかる貼り合わせウェーハの製造方法を示す工程断面図である。図1、図2に示すように、本実施形態においては、まず、活性層用ウェーハ1を準備し(ステップS101)、支持基板用ウェーハ2を準備する(ステップS102)。活性層用ウェーハ1及び支持基板用ウェーハ2は、特に限定されないが、本実施形態では、いずれもシリコン単結晶ウェーハである。特に、活性層用ウェーハ1は、抵抗率が100Ω・cm以上のものを用いることが好ましい。
ここで、DIC(Differential Interference Contrast)とは、KLA Tencor社製SP2のBright−Field−Channelで検出される欠陥を指し、幅が数十μm〜mmオーダーで、高さ数nmオーダーの段差欠陥を検出する特徴を有する。
上述した本実施形態の貼り合わせウェーハの製造方法によって得られる、貼り合わせウェーハは、後述の実施例でも示されるように、多結晶シリコンウェーハ層を有し、該多結晶シリコンウェーハ層は、厚さのばらつきΔtが5%以下、多結晶シリコンウェーハ層を研磨した後の、GBIRが0.2μm以下、SFQRが0.06μm以下である。
以下、本発明の実施例について説明するが、本発明は、以下の実施例に何ら限定されるものではない。
<厚さばらつきΔt>
研磨後の多結晶シリコン層について、赤外線分光装置(FT−IR)測定を行い、多結晶シリコン層の半径をRとしたときに、多結晶シリコン層の径方向の外周部3mmを除外したときの、径方向中心位置(1箇所)、径方向中心位置からR/2の距離にある4つの位置(中心位置からは90°ずつ、ずらして位置している)、及び、外周部から径方向内側に3mmの距離にある4つの位置(それぞれ、径方向中心位置と、上記径方向中心位置からR/2の距離にある4つの位置のそれぞれとの延長線上に位置する)の合計9つの位置の厚さを測定して、以下の式により算出したものである。
Δt={(最大厚さ−最小厚さ)/(最大厚さ+最小厚さ)}*100(%)
<微小欠陥数>
研磨後の多結晶シリコン層の表面を、ウェーハ表面検査装置(Surfscan SP2; KLA−Tencor社製)を用いて、DICモード(DIC法による測定モード)により測定した。
<平坦度>
多結晶シリコン層の研磨を行った後の、支持基板用ウェーハのGBIR、SFQRを、KLA社製 Wafersight2を用いて計測した。
2:支持基板用ウェーハ
3:多結晶シリコン層
4:絶縁膜
5:イオン注入層
6:貼り合わせウェーハ
Claims (4)
- 支持基板用ウェーハと、活性層用ウェーハとを、絶縁膜を介して貼り合わせて、貼り合わせウェーハを製造する方法であって、
前記支持基板用ウェーハの貼り合わせ面側に、多結晶シリコン層を堆積する、多結晶シリコン堆積工程と、
研磨布を用いて前記多結晶シリコン層の表面を研磨する、多結晶シリコン層研磨工程と、
前記支持基板用ウェーハ及び前記活性層用ウェーハの少なくともいずれかの貼り合わせ面に、前記絶縁膜を形成する、絶縁膜形成工程と、
前記絶縁膜を介して、前記支持基板用ウェーハの前記多結晶シリコン層の研磨面と、前記活性層用ウェーハとを、貼り合わせる、貼り合わせ工程と、を含み、
前記研磨布の沈み込み量を、
沈み込み量(μm)=研磨布の厚さ(μm)×圧縮率(%/(N/cm2))×荷重(N/cm2)で定義するとき、
前記研磨布の沈み込み量は、50〜90μmであり、且つ、前記研磨布の表面硬度(ASKER C)は、50〜60であることを特徴とする、貼り合わせウェーハの製造方法。 - 前記研磨布は、基材とナップ層とからなるスエードパッドである、請求項1に記載の貼り合わせウェーハの製造方法。
- 前記基材の厚さは、0.15〜0.20mmである、請求項2に記載の貼り合わせウェーハの製造方法。
- 支持基板用ウェーハ上に堆積された多結晶シリコンウェーハ層を有する、貼り合わせウェーハであって、
前記多結晶シリコンウェーハ層は、厚さのばらつきΔtが5%以下であり、
前記多結晶シリコンウェーハ層を研磨した後の、前記支持基板用ウェーハは、GBIRが0.2μm以下、SFQRが0.06μm以下であることを特徴とする、貼り合わせウェーハ。
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JP2018005914A JP6919579B2 (ja) | 2018-01-17 | 2018-01-17 | 貼り合わせウェーハの製造方法、貼り合わせウェーハ |
US16/962,311 US11211285B2 (en) | 2018-01-17 | 2019-01-08 | Method of producing bonded wafer and bonded wafer |
EP19740885.9A EP3742473A4 (en) | 2018-01-17 | 2019-01-08 | PROCESS FOR MANUFACTURING TIE SLICE, AND TIE SLICE |
CN201980008949.7A CN111788656B (zh) | 2018-01-17 | 2019-01-08 | 贴合晶圆的制造方法及贴合晶圆 |
PCT/JP2019/000240 WO2019142700A1 (ja) | 2018-01-17 | 2019-01-08 | 貼り合わせウェーハの製造方法、貼り合わせウェーハ |
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DE112021000907T5 (de) | 2020-04-08 | 2022-11-17 | Shin-Etsu Handotai Co., Ltd. | Verfahren zur Messung der Form von DIC-Defekten auf Silicium-Wafern und Polierverfahren |
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JP2006190703A (ja) * | 2004-12-28 | 2006-07-20 | Shin Etsu Handotai Co Ltd | エピタキシャルウェーハの製造方法及びエピタキシャルウェーハ |
JP2008207319A (ja) * | 2007-01-30 | 2008-09-11 | Toray Ind Inc | 研磨パッド |
JP2016136591A (ja) * | 2015-01-23 | 2016-07-28 | 信越半導体株式会社 | 貼り合わせsoiウェーハの製造方法 |
JP2017064894A (ja) * | 2015-10-02 | 2017-04-06 | ミクロ技研株式会社 | 研磨ヘッド及び研磨処理装置 |
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KR20200096645A (ko) | 2020-08-12 |
EP3742473A4 (en) | 2021-09-29 |
KR102410366B1 (ko) | 2022-06-16 |
WO2019142700A1 (ja) | 2019-07-25 |
CN111788656B (zh) | 2024-01-30 |
JP6919579B2 (ja) | 2021-08-18 |
US11211285B2 (en) | 2021-12-28 |
CN111788656A (zh) | 2020-10-16 |
EP3742473A1 (en) | 2020-11-25 |
US20200343130A1 (en) | 2020-10-29 |
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