CN111788656B - 贴合晶圆的制造方法及贴合晶圆 - Google Patents

贴合晶圆的制造方法及贴合晶圆 Download PDF

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CN111788656B
CN111788656B CN201980008949.7A CN201980008949A CN111788656B CN 111788656 B CN111788656 B CN 111788656B CN 201980008949 A CN201980008949 A CN 201980008949A CN 111788656 B CN111788656 B CN 111788656B
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佐藤洋三
小佐佐和明
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Abstract

在本发明的贴合晶圆的制造方法中,研磨布的沉入量为50~90μm,并且所述研磨布的表面硬度(ASKER C)为50~60。在本发明的贴合晶圆中,多晶硅层的厚度偏差Δt为5%以下,在研磨所述多晶硅层之后的支承基板用晶圆的GBIR为0.2μm以下,SFQR为0.06μm以下。

Description

贴合晶圆的制造方法及贴合晶圆
技术领域
本发明涉及一种贴合晶圆的制造方法及贴合晶圆。
背景技术
以往,提出有一种贴合晶圆,其通过在植入氧化膜的正下方设置作为载体的俘获层的多晶硅层而成(所谓的trap-rich型贴合SOI晶圆)。
上述贴合SOI晶圆隔着绝缘膜即氧化膜来贴合活性层用晶圆与具有多晶硅层的支承基板用晶圆而制作。在这种贴合晶圆中,有时会因多晶硅层的表面特性等而在贴合面上产生孔隙等。因此,为了抑制在贴合面上产生孔隙而进行多晶硅层的研磨(例如,参考专利文献1)。
现有技术文献
专利文献
专利文献1:日本特开2016-136591号公报
发明内容
发明所要解决的技术问题
在如上所述的多晶硅层的研磨中,希望研磨后的多晶硅层的厚度偏差小、微小缺陷少,并且支承基板用晶圆的平坦性高。
因此,本发明的目的在于提供一种贴合晶圆的制造方法及贴合晶圆,所述贴合晶圆的制造方法能够得到具有厚度偏差小、微小缺陷少、平坦性高的多晶硅层的支承基板用晶圆,所述贴合晶圆由具有厚度偏差小、微小缺陷少、平坦性高的多晶硅层的支承基板用晶圆构成。
用于解决技术问题的方案
本发明的主旨方案为如下。
本发明的贴合晶圆的制造方法是隔着绝缘膜来贴合支承基板用晶圆与活性层用晶圆而制造贴合晶圆的方法,所述贴合晶圆的制造方法的特征在于,包括:
多晶硅堆积工序,在所述支承基板用晶圆的贴合面侧堆积多晶硅层;
多晶硅层研磨工序,使用研磨布来研磨所述多晶硅层的表面;
绝缘膜形成工序,在所述支承基板用晶圆及所述活性层用晶圆中的至少一个晶圆的贴合面上形成所述绝缘膜;及
贴合工序,隔着所述绝缘膜来贴合所述支承基板用晶圆的所述多晶硅层的研磨面与所述活性层用晶圆,
当将所述研磨布的沉入量以沉入量(μm)=研磨布的厚度(μm)×压缩率(%/(N/cm2))×荷载(N/cm2)来定义时,
所述研磨布的沉入量为50~90μm,并且所述研磨布的表面硬度(ASKER C)为50~60。
在此,“研磨布的表面硬度(ASKER C)”通过ASKER C硬度计来测量。
在本发明的贴合晶圆的制造方法中,所述研磨布优选为由基材和绒毛层构成的绒面垫。
在上述情况下,所述基材的厚度优选为0.15~0.20mm。
本发明的贴合晶圆的特征在于,具有堆积于支承基板用晶圆上的多晶硅层,
所述多晶硅层的厚度偏差Δt为5%以下,
在研磨所述多晶硅层之后的所述支承基板用晶圆的GBIR为0.2μm以下,SFQR为0.06μm以下。
在此,关于研磨后的多晶硅层进行红外线分光装置(FT-IR)测定,当多晶硅层的半径为R时,测定排除多晶硅层的径向的外周部3mm时的径向中心位置(一个部位)、与径向中心位置相距R/2的4个位置(从中心位置分别偏移90°的位置)、以及与外周部向径向内侧相距3mm的4个位置(分别位于径向中心位置和与上述径向中心位置相距R/2的4个位置的延长线上)共计9个位置的厚度,并通过以下式计算出厚度偏差(Δt)。
Δt={(最大厚度-最小厚度)/(最大厚度+最小厚度)}*100(%)
并且,上述“GBIR”(Grobal Backside Ideal focal plane Range:全局平整度)、上述“SFQR”(Site Front least sQuares Range:局部平整度)分别使用KLA-Tencor公司制造:WaferSight2来测定。
发明效果
根据本发明,能够提供一种贴合晶圆的制造方法及贴合晶圆,所述贴合晶圆的制造方法能够得到具有厚度偏差小、微小缺陷少、平坦性高的多晶硅层的支承基板用晶圆,所述贴合晶圆具备具有厚度偏差小、微小缺陷少、平坦性高的多晶硅层的支承基板用晶圆。
附图说明
图1是本发明的一实施方式所涉及的贴合晶圆的制造方法的流程图。
图2是表示本发明的一实施方式所涉及的贴合晶圆的制造方法的工序截面图。
图3是表示研磨布的沉入量与多晶硅层的厚度偏差Δt的关系的图。
图4是表示研磨布的表面硬度(ASKER C)与DIC的关系的图。
图5是表示实施例的厚度偏差Δt的测定结果的图。
图6是表示实施例的DIC数量的图。
图7是表示实施例的GBIR测定结果的图。
图8是表示实施例的SFQR测定结果的图。
具体实施方式
以下,参考附图,对本发明的实施方式详细地举例说明。
<贴合晶圆的制造方法>
图1是本发明的一实施方式所涉及的贴合晶圆的制造方法的流程图。图2是表示本发明的一实施方式所涉及的贴合晶圆的制造方法的工序截面图。如图1、图2所示,在本实施方式中,首先准备活性层用晶圆1(步骤S101)、支承基板用晶圆2(步骤S102)。活性层用晶圆1及支承基板用晶圆2并不受特别的限定,但是在本实施方式中均为单晶硅晶圆。尤其,活性层用晶圆1优选使用电阻率为100Ω·cm以上的晶圆。
如图1、图2所示,在本实施方式中,对支承基板用晶圆2的单面进行研磨(步骤S103)。研磨能够以通常的方法来进行,例如能够以1次研磨、2次研磨、精抛这3个阶段来进行,并分别在通常的研磨条件下进行。另外,在支承基板用晶圆2的直径为300mm以上的情况下,能够进行双面研磨及单面研磨。
接着,如图1、图2所示,在支承基板用晶圆2上堆积多晶硅层3(多晶硅层堆积工序)(步骤S104)。多晶硅层3例如能够通过CVD法来堆积。多晶硅层的厚度优选为2~4μm。
接着,在本实施方式中,如图1、图2所示,使用规定的研磨布对支承基板用晶圆2的多晶硅层3的表面进行研磨(多晶硅层研磨工序)(步骤S105)。在此,在本实施方式中,在规定的研磨布的沉入量为50~90μm,并且研磨布的表面硬度(ASKER C)为50~60。另外,“沉入量”及“表面硬度(ASK ER C)”的定义为如上所述。
在本实施方式中,研磨布是由基材和绒毛层构成的绒面垫,绒毛层由2层构成。绒毛层也可以是1层或3层以上。基材例如可以由PET构成。基材厚度优选为0.15~0.20mm。绒毛层厚度(在多层的情况下为总厚度)优选为0.5~0.9mm左右,更优选为0.5~0.7mm左右。尤其,在绒毛层为2层的情况下,表层厚度优选为0.3mm~0.5mm左右,第2层(表层与基材之间的层)的厚度优选为0.15~0.20mm左右。这是因为它适合于上述沉入量及表面硬度。
在多晶硅层研磨工序(步骤S105)中,研磨剂能够使用胶体二氧化硅等任意的已知研磨剂,作为研磨条件,优选研磨压力为2500~3000N/cm2、研磨垫的转速为30~50rpm、工件的转速为30~50rpm、研磨余量为400nm以上。
另外,虽然在图1、图2中未示出,但是在多晶硅层研磨工序(步骤S105)之后,能够进行用于去除颗粒的清洗工序。
接着,在本实施方式中,如图1、图2所示,在活性层用晶圆1的贴合面上形成绝缘膜4(步骤S106)。例如,绝缘膜4可以是氧化膜。氧化膜例如能够通过热氧化处理的氧化膜生长而形成。另外,也能够由离子注入机从氧化膜4的上方注入氢离子或稀有气体离子以形成用于剥离的离子注入层5(参考图2)。在该情况下,能够调整离子注入加速电压等,以便能够得到目标SOI层的厚度。
接着,在本实施方式中,如图1、图2所示,隔着绝缘膜4(在该例中为氧化膜)来贴合支承基板用晶圆2的多晶硅层3的研磨面与活性层用晶圆1(步骤S107)。
接着,使已贴合的活性层用晶圆进薄膜化而形成SOI层(步骤S108)。例如,对已贴合的晶圆实施使离子注入层5产生微小气泡层的热处理(剥离热处理),并通过所产生的微小气泡层来剥离晶圆,从而制作在支承基板用晶圆2上形成绝缘膜4和SOI层的贴合晶圆6。
另外,如图2所示,在活性层用晶圆1与支承基板用晶圆2的贴合工序(步骤S107)之前,能够独立地进行与活性层用晶圆1有关的工序(步骤S101、步骤S106)及与支承基板用晶圆2有关的工序(步骤S102、步骤S103、步骤S104、步骤S105),因此在本发明中,关于与活性层用晶圆1有关的工序(步骤S101、步骤S106)和与支承基板用晶圆2有关的工序(步骤S102、步骤S103、步骤S104、步骤S105)的工序顺序,可以先进行任一工序,也可以同时并行进行。
以下,对本实施方式的贴合晶圆的制造方法的作用效果进行说明。图3是表示研磨布的沉入量与多晶硅层的厚度偏差Δt的关系的图(研磨压力为2700N/cm2)。图4是表示研磨布的表面硬度(ASKER C)与DIC缺陷数(每个晶圆的微小缺陷数)的关系的图。
在此,DIC(Differential Interference Contrast:差分干扰对比)是指,由KLA-Tencor公司制造的SP2的Bright-Field-Channel检测出的缺陷,其特征在于,检测宽度为几十微米~毫米级、高度为几纳米级的台阶差缺陷。
如图3所示,可知通过使用沉入量小的(尤其为90μm以下)研磨布而能够减小多晶硅层的厚度偏差Δt。可以认为这是因为通过使研磨面内的应力分布均匀而能够进行更平滑的研磨。关于平坦度也可以认为是相同的。
另一方面,如图4所示,可知若研磨布的表面硬度大,则导致DIC缺陷增大。可以认为这是因为虽然在多晶硅层的表面存在晶界,但是在使用表面硬度大的研磨布的情况下,研磨时无法追踪到晶界内部,因此无法有效地去除晶界内部的氧化膜。因此,例如为了减少沉入量而只是使用硬度大的研磨布,就会导致DIC缺陷增大。
相比之下,在本实施方式中,在使用规定的研磨布对支承基板用晶圆2的多晶硅层3的表面进行研磨的工序(步骤S105)中,作为规定的研磨布而使用研磨布的沉入量为50~90μm,研磨布的表面硬度(ASKER C)为50~60的研磨布。由此,能够减小研磨后的多晶硅的厚度偏差,减少微小缺陷,并提高研磨多晶硅层3之后的支承基板用晶圆2的平坦度。
在本发明的贴合晶圆的制造方法中,研磨布优选为由基材和绒毛层构成的绒面垫。这是因为它适合于上述沉入量及表面硬度(ASKER C)。
此时,研磨布的基材厚度优选为0.15~0.20mm。这是因为它适合于上述沉入量及表面硬度(ASKER C)。作为基材的材质,优选采用PET。
<贴合晶圆>
通过上述本实施方式的贴合晶圆的制造方法而得到的贴合晶圆如后述实施例也所示具有多晶硅层,该多晶硅层的厚度偏差Δt为5%以下,研磨多晶硅层之后的GBIR为0.2μm以下,SFQR为0.06μm以下。
以上,对本发明的实施方式进行了说明,但是本发明并不受上述实施方式的任何限定。例如,在上述实施方式中,将绝缘膜4仅形成于活性层用晶圆1侧,但是也可以将绝缘膜4仅形成于支承基板用晶圆2,还可以形成于活性层用晶圆1和支承基板用晶圆2两者。此外,本发明能够适用于以多晶硅层的研磨面为贴合面的各种贴合晶圆的制造方法中。尤其,能够适合使用于trap-ric h型贴合SOI晶圆的制造中。
以下,对本发明的实施例进行说明,但是本发明并不受以下实施例的任何限定。
实施例
为了确认本发明的效果而进行了使用单片式研磨机对研磨多晶硅层的试验。多晶硅层为p型,研磨前的厚度为780μm左右。研磨由预研磨和精抛构成,预研磨条件分为发明例和比较例。
在发明例中,作为研磨布而使用了绒面垫(绒毛层2层和基材硬质塑胶板)。绒面垫厚度为0.87mm(与基材相邻的绒毛层的厚度为0.30mm,表层侧的绒毛层的厚度为0.40mm,基材硬质塑胶板的厚度为0.17mm),沉入量为83.85μm,表面硬度(ASKER C)为59.5。研磨条件为研磨垫及工件的转速为32rpm,加工压力为2700N/cm2。研磨剂使用了胶体二氧化硅。研磨余量为400nm以上。
作为Δt、GBIR、SFQR的比较例,在比较例1中使用了厚度或硬度不同的绒面垫。研磨垫的厚度为1.07mm,沉入量为109.2μm,表面硬度(ASKER C)为50.5。研磨垫及工件的转速为32rpm,将加工压力为2700N/cm2。并且,作为DIC质量的比较例,在比较例2中使用了研磨垫的厚度为0.72mm、沉入量为54.6μm、表面硬度(ASKER C)为68.5的绒面垫。另外,比较例1及比较例2与发明例的研磨垫的厚度差取决于与基材相邻的绒毛层的厚度差。
以下,对各评价项目及评价方法进行说明。
<厚度偏差Δt>
关于研磨后的多晶硅层进行红外线分光装置(FT-IR)测定,当多晶硅层的半径为R时,测定排除多晶硅层的径向的外周部3mm时的径向中心位置(一个部位)、与径向中心位置相距R/2的4个位置(从中心位置分别偏移90°的位置)、以及与外周部向径向内侧相距3mm的4个位置(分别位于径向中心位置和与上述径向中心位置相距R/2的4个位置的延长线上)共计9个位置的厚度,并通过以下式算出。
Δt={(最大厚度-最小厚度)/(最大厚度+最小厚度)}*100(%)
<微小缺陷数>
使用晶圆表面检查装置(Surfscan SP2;KLA-Tencor公司制造),通过DIC模式(根据DIC法的测定模式)测定出研磨后的多晶硅层的表面。
<平坦度>
使用KLA-Tencor公司制造的Wafersight2测量研磨多晶硅层之后的支承基板用晶圆的GBIR、SFQR。
图5是表示实施例的厚度偏差Δt的测定结果的图。图6是表示实施例的DIC测定结果的图。图7是表示实施例的GBIR测定结果的图。图8是表示实施例的SFQR测定结果的图。
如图5~图8所示,在发明例中,Δt为5%以下,GBIR为0.2μm以下,SFQR为0.06μm以下。与比较例相比,在本发明例中能够得到厚度偏差更小、DIC缺陷更少、平坦度更高的多晶硅层(研磨后)。
附图标记说明
1-活性层用晶圆,2-支承基板用晶圆,3-多晶硅层,4-绝缘膜,5-离子注入层,6-贴合晶圆。

Claims (3)

1.贴合晶圆的制造方法,其为隔着绝缘膜来贴合支承基板用晶圆和活性层用晶圆而制造贴合晶圆的方法,所述贴合晶圆的制造方法的特征在于,包括:
多晶硅堆积工序,在所述支承基板用晶圆的贴合面侧堆积多晶硅层;
多晶硅层研磨工序,使用研磨布来研磨所述多晶硅层的表面;
绝缘膜形成工序,在所述支承基板用晶圆及所述活性层用晶圆中的至少一个晶圆的贴合面上形成所述绝缘膜;及
贴合工序,隔着所述绝缘膜来贴合所述支承基板用晶圆的所述多晶硅层的研磨面与所述活性层用晶圆,
当将所述研磨布的沉入量以沉入量=研磨布的厚度×压缩率×荷载来定义时,所述研磨布的沉入量为50~90μm,并且所述研磨布的表面硬度为50~59.5,该表面硬度为ASKER C硬度,其中沉入量的单位为μm,研磨布的厚度的单位为μm,压缩率的单位为%/(N/cm2),荷载的单位为N/cm2
2.根据权利要求1所述的贴合晶圆的制造方法,其中,
所述研磨布是由基材和绒毛层构成的绒面垫。
3.根据权利要求2所述的贴合晶圆的制造方法,其中,
所述基材的厚度为0.15~0.20mm。
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101091237A (zh) * 2004-12-28 2007-12-19 信越半导体股份有限公司 磊晶晶片的制造方法及磊晶晶片
JP2008207319A (ja) * 2007-01-30 2008-09-11 Toray Ind Inc 研磨パッド
JP2014236147A (ja) * 2013-06-04 2014-12-15 株式会社Sumco 貼合せsoiウェーハの製造方法
JP2017064894A (ja) * 2015-10-02 2017-04-06 ミクロ技研株式会社 研磨ヘッド及び研磨処理装置
CN107112204A (zh) * 2015-01-23 2017-08-29 信越半导体株式会社 贴合式soi晶圆的制造方法
WO2017212812A1 (ja) * 2016-06-06 2017-12-14 信越半導体株式会社 貼り合わせsoiウェーハの製造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19956250C1 (de) * 1999-11-23 2001-05-17 Wacker Siltronic Halbleitermat Kostengünstiges Verfahren zur Herstellung einer Vielzahl von Halbleiterscheiben
KR100909605B1 (ko) 2005-03-08 2009-07-27 도요 고무 고교 가부시키가이샤 연마 패드 및 그 제조 방법
JP4593643B2 (ja) 2008-03-12 2010-12-08 東洋ゴム工業株式会社 研磨パッド
JP5795461B2 (ja) * 2009-08-19 2015-10-14 株式会社Sumco エピタキシャルシリコンウェーハの製造方法
FR2953640B1 (fr) * 2009-12-04 2012-02-10 S O I Tec Silicon On Insulator Tech Procede de fabrication d'une structure de type semi-conducteur sur isolant, a pertes electriques diminuees et structure correspondante
JP6491812B2 (ja) 2013-10-02 2019-03-27 株式会社Sumco メンブレン、研磨ヘッド、ワークの研磨装置及び研磨方法、並びに、シリコンウェーハ
JP6100200B2 (ja) * 2014-04-24 2017-03-22 信越半導体株式会社 貼り合わせsoiウェーハの製造方法
WO2017013935A1 (ja) 2015-07-17 2017-01-26 株式会社フジミインコーポレーテッド 研磨パッド及び研磨方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101091237A (zh) * 2004-12-28 2007-12-19 信越半导体股份有限公司 磊晶晶片的制造方法及磊晶晶片
JP2008207319A (ja) * 2007-01-30 2008-09-11 Toray Ind Inc 研磨パッド
JP2014236147A (ja) * 2013-06-04 2014-12-15 株式会社Sumco 貼合せsoiウェーハの製造方法
CN107112204A (zh) * 2015-01-23 2017-08-29 信越半导体株式会社 贴合式soi晶圆的制造方法
JP2017064894A (ja) * 2015-10-02 2017-04-06 ミクロ技研株式会社 研磨ヘッド及び研磨処理装置
WO2017212812A1 (ja) * 2016-06-06 2017-12-14 信越半導体株式会社 貼り合わせsoiウェーハの製造方法

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