JP2019106425A - 絶縁ゲート型半導体装置及びその製造方法 - Google Patents
絶縁ゲート型半導体装置及びその製造方法 Download PDFInfo
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Abstract
Description
第2実施形態に係る絶縁ゲート型半導体装置は、図10に示すように、第1導電型(n型)のドリフト層1と、ドリフト層1上に選択的に設けられ、第2導電型(p+型)のベース領域3a,3bを備える。ベース領域3a,3bの上部には、ドリフト層1よりも高不純物密度で第1導電型の主電極領域(ソース領域)4a〜4dが設けられている。なお、4b,4dは電流経路として使用しないため、設けられていなくてもよい。
第3実施形態に係る絶縁ゲート型半導体装置は、図14に示すように、第1導電型(n型)のドリフト層1と、ドリフト層1上に選択的に設けられ、第2導電型(p型)のベース領域3a,3bを備える。ベース領域3a,3bの上部には、ドリフト層1よりも高不純物密度で第1導電型(n+型)の主電極領域(ソース領域)4a〜4cが設けられている。なお、ソース領域4bは電流経路として使用しないため、設けられていなくてもよい。ソース領域4a〜4cの上面から、ソース領域4a,4bを貫通してドリフト層1に達するトレンチ10が設けられている。トレンチ10の一方の側壁面はソース領域4a及びベース領域3aに接し、他方の側壁面はソース領域4bに接する。
第4実施形態に係る絶縁ゲート型半導体装置は、図27に示すように、4本のストライプ状のトレンチ10a〜10dをそれぞれ有する複数のストライプ状の単位セルC1〜C4の配列構造を有する。第4実施形態に係る絶縁ゲート型半導体装置は、第1導電型(n型)のドリフト層1と、ドリフト層1上に配置された第2導電型(p型)のベース領域3a,3bを備える。ベース領域3a,3bの上部には、ドリフト層1よりも高不純物密度で第1導電型(n+型)の主電極領域(ソース領域)41,43が設けられている。
上記のように、本発明は第1〜第4実施形態によって記載したが、この開示の一部をなす論述及び図面は本発明を限定するものであると理解すべきではない。この開示から当業者には様々な代替実施形態、実施例及び運用技術が明らかとなろう。
2,2a,2b,2c,2d,2e,21,21a,21b,22a,22b,23,23a,23b…ゲート保護領域
2g,2h,2i…ベースコンタクト領域
2x,2y…動作抑制領域
3,3a,3b,3c,3d,3e…ベース領域
4,4a,4b,4c,4d,4e,4f,4g,4h,4i,4j,41,41a,41b,42a,42b,43,43a,43b…ソース領域
5,5a,5b,5c,5d,5e,5f…ゲート絶縁膜
6,6a,6b,6c,6d,6e,6f…ゲート電極
7…層間絶縁膜
8…ソース電極
8a…凸部
9…ドレイン領域
10a,10b,10c,10d,10e,10f…トレンチ
11…ドレイン電極
12a,12b…電流拡散層
31…フォトレジスト膜
Claims (26)
- チップ構造の基準面に対し第1の傾斜角をなす第1側壁面と、該第1側壁面に対向し前記基準面に対し前記第1の傾斜角とは異なる第2の傾斜角をなす第2側壁面で両側壁を定義した複数のトレンチを前記チップ構造に配列した絶縁ゲート型半導体装置であって、
前記複数のトレンチに含まれる第1のトレンチに絶縁ゲート型電極構造を設けた第1の単位セルであって、前記第1のトレンチの第1側壁面に接した第1導電型の主電極領域、該主電極領域の下面と前記第1側壁面に接した第2導電型のベース領域、該ベース領域の下面と前記第1側壁面に接した前記主電極領域より低不純物密度で第1導電型のドリフト層、前記第1のトレンチの前記第2側壁面及び底面に接し、前記ベース領域よりも高不純物密度で第2導電型のゲート保護領域を有する第1の単位セルと、
前記複数のトレンチに含まれる第2のトレンチに絶縁ゲート型電極構造を設けた第2の単位セルであって、前記ドリフト層の上部に埋め込まれ、前記第2のトレンチの第1側壁面及び第2側壁面に接した第2導電型で、前記ベース領域よりも高不純物密度の動作抑制領域を有する第2の単位セルと
を備え、前記第2の単位セルが、前記複数のトレンチの配列の一端に位置する前記第2のトレンチを含むように配置されることを特徴とする絶縁ゲート型半導体装置。 - 前記第2の単位セルに前記第1の単位セルが隣接して配置され、前記第1の単位セルの前記ゲート保護領域と前記第2の単位セルの前記動作抑制領域の間に前記ドリフト層、前記第1の単位セルの前記主電極領域及び前記ベース領域が存在することを特徴とする請求項1に記載の絶縁ゲート型半導体装置。
- 前記第2の単位セルに前記第1の単位セルが隣接して配置され、前記第1の単位セルの前記ゲート保護領域と前記第2の単位セルの前記動作抑制領域とが共通の半導体領域からなることを特徴とする請求項1に記載の絶縁ゲート型半導体装置。
- 前記第2の単位セルが、前記複数のトレンチの配列の両端に位置する前記第2のトレンチを含むようにそれぞれ配置されることを特徴とする請求項1〜3のいずれか1項に記載の絶縁ゲート型半導体装置。
- 前記第2の単位セルが、前記複数のトレンチの配列の一端に位置する隣接する前記第2のトレンチをそれぞれ含むように複数隣接して配置されることを特徴とする請求項1〜4のいずれか1項に記載の絶縁ゲート型半導体装置。
- チップ構造の基準面に対し第1の傾斜角をなす第1側壁面と、該第1側壁面に対向し前記基準面に対し前記第1の傾斜角とは異なる第2の傾斜角をなす第2側壁面で両側壁を定義したトレンチの内側に配置された絶縁ゲート型電極構造と、
前記トレンチの第1側壁面に接した第1導電型の主電極領域と、
該主電極領域の下面と前記第1側壁面に接した第2導電型のベース領域と、
該ベース領域の下面と前記第1側壁面に接した前記主電極領域より低不純物密度で第1導電型のドリフト層と、
前記トレンチの前記第2側壁面及び底面に接し、前記ベース領域よりも高不純物密度で第2導電型のゲート保護領域と、
前記主電極領域と接した主電極とを有する単位セルを複数備え、
隣接する前記単位セルの間に位置する前記ドリフト層と前記主電極により構成されるショットキーバリアダイオードを内蔵することを特徴とする絶縁ゲート型半導体装置。 - 前記主電極領域の上面と同一の水平レベルに位置する前記ドリフト層の上面と前記主電極により前記ショットキーバリアダイオードのショットキー接合が構成されることを特徴とする請求項6に記載の絶縁ゲート型半導体装置。
- 前記主電極が、前記ドリフト層に前記トレンチの底面と同一の深さまで埋め込まれた凸部を有し、
前記凸部の底面と前記ドリフト層とにより前記ショットキーバリアダイオードのショットキー接合が構成されることを特徴とする請求項6に記載の絶縁ゲート型半導体装置。 - 前記主電極が、前記ドリフト層に前記トレンチの底面と同一の深さまで埋め込まれた凸部を有し、
前記凸部の側面と前記ドリフト層とにより前記ショットキーバリアダイオードのショットキー接合が構成されることを特徴とする請求項6に記載の絶縁ゲート型半導体装置。 - 前記主電極が前記ドリフト層に前記トレンチの底面と同一の深さまで埋め込まれた凸部を有し、
前記主電極領域の上面と同一の水平レベルに位置する前記主電極の下面、前記凸部の側面及び底面と、前記ドリフト層とにより前記ショットキーバリアダイオードのショットキー接合が構成されることを特徴とする請求項6に記載の絶縁ゲート型半導体装置。 - チップ構造の基準面に対し第1の傾斜角をなす第1側壁面と、該第1側壁面に対向し前記基準面に対し前記第1の傾斜角とは異なる第2の傾斜角をなす第2側壁面で両側壁を定義したトレンチの内側に配置された絶縁ゲート型電極構造と、
前記トレンチの第1側壁面に接した高不純物密度で第1導電型の主電極領域と、
該主電極領域の下面と前記第1側壁面に接した第2導電型のベース領域と、
該ベース領域の下面と前記第1側壁面に接した前記主電極領域より低不純物密度で第1導電型のドリフト層と、
前記トレンチの前記第2側壁面及び底面に接し、前記ベース領域よりも高不純物密度で第2導電型のゲート保護領域と、
前記トレンチから離間して前記ゲート保護領域に接し、前記ベース領域よりも高不純物密度で第2導電型のベースコンタクト領域と
を備えることを特徴とする絶縁ゲート型半導体装置。 - 前記ゲート保護領域の不純物密度が、前記ベースコンタクト領域の不純物密度よりも高いことを特徴とする請求項11に記載の絶縁ゲート型半導体装置。
- 前記ゲート保護領域の前記トレンチの底面に接する端部の側面が、前記トレンチの前記第1側壁面の上端と前記ゲート保護領域の前記トレンチの底面に接する端部を結ぶ直線に平行に傾斜することを特徴とする請求項11又は12に記載の絶縁ゲート型半導体装置。
- 前記ゲート保護領域の底面が、前記ベースコンタクト領域の底面よりも浅いことを特徴とする請求項11〜13のいずれか1項に記載の絶縁ゲート型半導体装置。
- 第1導電型のドリフト層と、
前記ドリフト層上に設けられた第2導電型のベース領域と、
前記ベース領域の上部に設けられ、前記ドリフト層よりも高不純物密度で第1導電型の主電極領域と、
前記主電極領域及び前記ベース領域に一方の側壁面が接するように、ストライプ状のトレンチの内側に設けられた絶縁ゲート型電極構造と、
前記トレンチの底面及び他方の側壁面に接するように前記ドリフト層上にストライプ状に設けられ、前記ベース領域よりも高不純物密度で第2導電型のゲート保護領域
とを備えるストライプ状の単位セルが複数配列され、
隣接する前記単位セルの前記トレンチ間に共通の前記ベース領域を挟む構造と、隣接する前記単位セルの前記トレンチ間に共通の前記ゲート保護領域を挟む構造とを交互に繰り返し、
前記ゲート保護領域が前記トレンチの長手方向に沿って間欠的に配列されていることを特徴とする絶縁ゲート型半導体装置。 - 前記隣接するセルにおいて、前記長手方向に沿った前記ゲート保護領域の配列位置が、前記長手方向に直交する方向において同じであることを特徴とする請求項15に記載の絶縁ゲート型半導体装置。
- 前記隣接するセルにおいて、前記長手方向に沿った前記ゲート保護領域の配列位置が、前記長手方向に直交する方向において異なることを特徴とする請求項15に記載の絶縁ゲート型半導体装置。
- 前記側壁面がm面であることを特徴とする請求項15に記載の絶縁ゲート型半導体装置。
- 前記ゲート保護領域の前記トレンチの長手方向の幅が前記トレンチ間の幅以下であることを特徴とする請求項15に記載の絶縁ゲート型半導体装置。
- 第1導電型のドリフト層上に第2導電型のベース領域を形成する工程と、
前記ベース領域の上部に、前記ドリフト層よりも高不純物密度で第1導電型の主電極領域を形成する工程と、
前記主電極領域が形成されたチップ構造の基準面に対し第1の傾斜角をなす第1側壁面と、該第1側壁面に対向し前記基準面に対し前記第1の傾斜角とは異なる第2の傾斜角をなす第2側壁面で両側壁を定義したトレンチを前記ドリフト層に到達するまで形成し、前記主電極領域及び前記ベース領域を前記第1側壁面に露出させる工程と、
前記トレンチの底面及び前記第1側壁面に斜めにイオン注入することにより、前記トレンチの前記底面及び前記第1側壁面に接した第2導電型のゲート保護領域を形成する工程と、
前記トレンチの内側に絶縁ゲート型電極構造を形成する工程と
を含むことを特徴とする絶縁ゲート型半導体装置の製造方法。 - 前記第1側壁面がa面であることを特徴とする請求項20に記載の絶縁ゲート型半導体装置の製造方法。
- 前記第1側壁面は、前記第2側壁面よりSi面側に傾斜角が小さいことを特徴とする請求項20に記載の絶縁ゲート型半導体装置の製造方法。
- 前記第1側壁面がa面であることを特徴とする請求項1,6および11のいずれか1項に記載の絶縁ゲート型半導体装置。
- 前記第1側壁面は、前記第2側壁面よりSi面側に傾斜角が小さいことを特徴とする請
求項1,6および11のいずれか1項に記載の絶縁ゲート型半導体装置。 - SiCを用いた絶縁ゲート型半導体装置であることを特徴とする請求項1,6、11および15のいずれか1項に記載の絶縁ゲート型半導体装置。
- SiCを用いた絶縁ゲート型半導体装置の製造方法であることを特徴とする請求項20に記載の絶縁ゲート型半導体装置の製造方法。
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US16/170,530 US10490633B2 (en) | 2017-12-11 | 2018-10-25 | Insulated-gate semiconductor device and method of manufacturing the same |
US16/661,925 US10672874B2 (en) | 2017-12-11 | 2019-10-23 | Insulated-gate semiconductor device and method of manufacturing the same |
US16/844,113 US11177350B2 (en) | 2017-12-11 | 2020-04-09 | Insulated-gate semiconductor device and method of manufacturing the same |
US17/487,563 US11610969B2 (en) | 2017-12-11 | 2021-09-28 | Insulated-gate semiconductor device |
JP2021207299A JP7331914B2 (ja) | 2017-12-11 | 2021-12-21 | 絶縁ゲート型半導体装置及びその製造方法 |
JP2022079018A JP7384236B2 (ja) | 2017-12-11 | 2022-05-12 | 絶縁ゲート型半導体装置 |
US18/097,586 US11798993B2 (en) | 2017-12-11 | 2023-01-17 | Insulated-gate semiconductor device and method of manufacturing the same |
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WO2021161436A1 (ja) * | 2020-02-13 | 2021-08-19 | 三菱電機株式会社 | 炭化珪素半導体装置および電力変換装置の製造方法 |
WO2023047878A1 (ja) * | 2021-09-22 | 2023-03-30 | 株式会社日立製作所 | 炭化ケイ素半導体装置およびその製造方法 |
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US11798993B2 (en) | 2023-10-24 |
US20190181229A1 (en) | 2019-06-13 |
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US20240014270A1 (en) | 2024-01-11 |
US10490633B2 (en) | 2019-11-26 |
US11610969B2 (en) | 2023-03-21 |
JP7151076B2 (ja) | 2022-10-12 |
US10672874B2 (en) | 2020-06-02 |
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US11177350B2 (en) | 2021-11-16 |
US20200058740A1 (en) | 2020-02-20 |
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