JP2019067973A - 電子部品内蔵基板及びその製造方法 - Google Patents
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- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
- H01L21/4882—Assembly of heatsink parts
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Abstract
Description
図2〜図24は実施形態の電子部品内蔵基板の製造方法を説明するための図、図25〜図27は実施形態の電子部品内蔵基板を示す図である。
Claims (11)
- 第1絶縁層と、
前記第1絶縁層の上に形成された金属層と、
前記金属層の上に配置された発熱する第1電子部品と、
前記第1絶縁層及び前記金属層の上に形成され、前記第1電子部品を埋め込む第2絶縁層と、
前記第2絶縁層に形成され、前記金属層の一部を露出させる開口部と、
前記第2絶縁層の上方に配置された第2電子部品と、
前記開口部内の前記金属層に接続され、かつ、前記第2電子部品の上面に接続された放熱部材と
を有することを特徴とする電子部品内蔵基板。 - 前記第1絶縁層の上に形成された第1配線層を有し、
前記金属層及び前記第1配線層は、シード層と、前記シード層の上に配置された電解めっき層とから形成されることを特徴とする請求項1に記載の電子部品内蔵基板。 - 前記絶縁層の上に形成された第1配線層を有し、
前記第1配線層は、シード層と、前記シード層の上に配置された電解めっき層とから形成され、
前記金属層は、前記第1絶縁層の上に接着された金属板からなることを特徴とする請求項1に記載の電子部品内蔵基板。 - 前記金属層は、前記第1配線層よりも厚みが厚いことを特徴とする請求項2又は3に記載の電子部品内蔵基板。
- 前記第1電子部品は、前記第2電子部品の真下の領域に配置されていることを特徴とする請求項1乃至4のいずれか一項に記載の電子部品内蔵基板。
- 前記第1電子部品の下面が前記金属層に接着され、前記第1電子部品は上面に接続端子を備え、
前記第2絶縁層の上に形成された第2配線層を有し、
前記第2電子部品は前記第2配線層に電気的に接続されており、
前記第2配線層は、前記第2絶縁層に形成されたビアホール内のビア導体を介して前記第1電子部品の接続端子及び前記第1配線層に接続されていることを特徴とする請求項1乃至5のいずれか一項に記載の電子部品内蔵基板。 - 第1絶縁層の上に金属層を形成する工程と、
前記金属層の上に、発熱する第1電子部品を配置する工程と、
前記第1絶縁層及び前記金属層の上に、前記第1電子部品を埋め込む第2絶縁層を形成する工程と、
前記第2絶縁層に、前記金属層の一部を露出させる開口部を形成する工程と、
前記第2絶縁層の上方に第2電子部品を配置する工程と、
前記開口部内の前記金属層に接続され、かつ、第2電子部品の上面に接続される放熱部材を配置する工程と
を有することを特徴とする電子部品内蔵基板の製造方法。 - 前記第1絶縁層の上に金属層を形成する工程において、前記第1絶縁層の上に第1配線層を同時に形成し、
前記金属層及び前記第1配線層は、
前記第1絶縁層の上にシード層を形成する工程と、
前記シード層の上に、開口部を備えためっきレジスト層を形成する工程と、
電解めっきにより、前記めっきレジスト層の開口部に金属めっき層を形成する工程と、
前記めっきレジスト層を除去する工程と、
前記金属めっき層をマスクにして前記シード層をエッチングする工程と
を含む方法により形成されることを特徴とする請求項7に記載の電子部品内蔵基板の製造方法。 - 前記第1絶縁層の上に金属層を形成する工程は、前記第1絶縁層の上に第1配線層を形成することを含み、
前記第1配線層は、
前記第1絶縁層の上にシード層を形成する工程と、
前記シード層の上に、開口部を備えためっきレジスト層を形成する工程と、
電解めっきにより、前記めっきレジスト層の開口部に金属めっき層を形成する工程と、
前記めっきレジスト層を除去する工程と、
前記金属めっき層をマスクにして前記シード層をエッチングする工程と
を含む方法により形成され、
前記第1配線層を形成した後に、
前記第1絶縁層の上に金属板を接着して前記金属層を得ることを特徴とする請求項7に記載の電子部品内蔵基板の製造方法。 - 前記金属層を形成する工程において、
前記金属層は、前記第1配線層よりも厚みが厚く設定されることを特徴とする請求項8又は9に記載の電子部品内蔵基板の製造方法。 - 前記第1電子部品を配置する工程及び前記第2電子部品を配置する工程において、
前記第1電子部品は、前記第2電子部品の真下の領域に配置されることを特徴とする請求項7乃至10のいずれか一項に記載の電子部品内蔵基板の製造方法。
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JP7331591B2 (ja) | 2019-09-27 | 2023-08-23 | 株式会社デンソーウェーブ | 電気回路基板ユニット、及びプログラマブルロジックコントローラ |
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US20200161206A1 (en) * | 2018-11-20 | 2020-05-21 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure and semiconductor manufacturing process |
CN111211059B (zh) * | 2018-11-22 | 2023-07-04 | 矽品精密工业股份有限公司 | 电子封装件及其制法与散热件 |
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