JP2019029401A - 電子素子実装用基板、電子装置および電子モジュール - Google Patents
電子素子実装用基板、電子装置および電子モジュール Download PDFInfo
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Abstract
Description
、電極とほかの部材を接続するための半田が露出した導体層を流れ、隣り合う電極間のショートまたは、他の部品とのショートが発生することを低減させることが可能となる。さらに、上述した電子素子実装用基板を備えた電子装置を用いることによって、薄型化・小型化した場合においてもショートを低減させ誤作動が発生することを低減させることが可能な電子装置および電子モジュールを提供することが可能となる。
以下、本発明のいくつかの例示的な実施形態について図面を参照して説明する。なお、以下の説明では、電子素子実装用基板に電子素子が実装された構成を電子装置とする。また、電子素子実装用基板の上面側に位置するようにまたは電子装置を囲んで設けられた筐体または部材を有する構成を電子モジュールとする。電子素子実装用基板、電子装置および電子モジュールは、いずれの方向が上方若しくは下方とされてもよいが、便宜的に、直交座標系xyzを定義するとともに、z方向の正側を上方とする。
図1〜図4を参照して本発明の第1の実施形態における電子モジュール31、電子装置21、および電子素子実装用基板1について、図3を参照して本発明の第1の実施形態における電子素子実装用基板1の内層について、図4に要部Aの説明をする。本実施形態における電子装置21は、電子素子実装用基板1と電子素子10とを備えている。なお、本実施形態では図1では電子装置21を示しており、図2では電子モジュール31を示しており、図3〜図4では電子素子実装用基板1の内層およびその要部の拡大図を示している。また、図1〜図2では導体層5をドットおよび点線で、図3〜図4ではドットおよび実線で示している。
。
の導体層5の外縁5aは平面視において、基板2の外縁よりも内側に位置している。これにより、基板2の側面に導体層5を露出させることを低減させることが可能となる。よって、基板2の凹部7の電極7aと他の部材を接続するための半田が露出した導体層5上に流れることを低減させることができ、隣り合う凹部7(電極7a)のショートまたは他の部品とのショートが発生を低減させることが可能となる。
図1に電子装置21の例を示す。電子装置21は、電子素子実装用基板1と、電子素子実装用基板1の上面または下面に実装された電子素子10を備えている。
合する蓋体接合材14と同じ材料から成る場合がある。このとき、蓋体接合材14を厚く設けることで、接着の効果と枠状体(蓋体12を支える部材)としての効果を併せ持つことが可能となる。このときの蓋体接合材14は例えば熱硬化性樹脂または低融点ガラスまたは金属成分から成るろう材等が挙げられる。また、枠状体と蓋体12とが同じ材料から成る場合もあり、このときは枠状体と蓋体12は同一個体として構成されていてもよい。
図2に電子素子実装用基板1を用いた電子モジュール31の一例を示す。電子モジュール31は、電子装置21と電子装置21の上面または電子装置21を覆うように設けられた筐体32とを有している。なお、以下に示す例では説明のため撮像モジュールを例に説明する。
次に、本実施形態の電子素子実装用基板1および電子装置21の製造方法の一例について説明する。なお、下記で示す製造方法の一例は、基板2を多数個取り配線基板を用いた製造方法である。
結助材としてシリカ(SiO2)、マグネシア(MgO)またはカルシア(CaO)等の粉末を添加し、さらに適当なバインダー、溶剤および可塑剤を添加し、次にこれらの混合物を混錬してスラリー状となす。その後、ドクターブレード法またはカレンダーロール法等の成形方法によって多数個取り用のセラミックグリーンシートを得る。
さく切り込んだりすることによって形成してもよい。なお、上述した多数個取り配線基板を複数の基板2(電子素子実装用基板1)に分割する前もしくは分割した後に、それぞれ電解または無電解めっき法を用いて、電極パッド3、外部接続用パッドおよび露出した配線導体にめっきを被着させてもよい。
次に、本発明の第2の実施形態による電子素子実装用基板1について、図5〜図6を参照しつつ説明する。本実施形態における電子素子実装用基板1において、第1の実施形態の電子素子実装用基板1と異なる点は、基板2は複数の導体層5を有している点、電極7aの形状が異なる点である。なお、図5では導体層5をドットおよび点線で、図6ではドットおよび実線で示している。
次に、本発明の第3の実施形態による電子素子実装用基板1について、図7〜図10を参照しつつ説明する。なお、図7および図8は本実施形態における電子素子実装用基板1、電子装置および電子モジュールの形状を示しており、図9および図10の内層を示す。本実施形態における電子素子実装用基板1において、第1の実施形態の電子素子実装用基板1と異なる点は、基板2が貫通孔を有する(電子素子10の実装方法が異なる)点、凹部7が基板2の上面から下面まで連続していない点である。なお図7および図8では導体層5をドットおよび破線で示している。また、図9および図10では導体層5をドットおよび実線で示している。
子素子接続材13で接続されていてもよい。
から水分が入り込み、複数の導体層5間においてマイグレーションが発生することを低減させることが可能となる。
2・・・・基板
2a・・・貫通孔
3・・・・電極パッド
5・・・・導体層
5a・・・導体層の外縁
7・・・・凹部
7a・・・電極
10・・・電子素子
12・・・蓋体
13・・・電子素子接続材
14・・・蓋体接合材
31・・・電子モジュール
32・・・筐体
Claims (7)
- 上下に積層された複数の層と、前記複数の層の間に位置した複数の導体層と、前記複数の層の側面に連続して位置した凹部と、を有する電子素子が実装される基板と、
前記凹部内に位置するとともに、前記凹部における前記少なくとも1つの導体層の端部を覆った電極と、を備えており、
前記導体層と、前記電極とは、異なる金属材料を含有しているとともに、平面視において、前記導体層の外縁は、前記基板の外縁よりも内側に位置していることを特徴とする電子素子実装用基板。 - 前記複数の導体層を構成する材料は、前記電極を構成する材料よりも銅の含有率が高いことを特徴とする請求項1に記載の電子素子実装用基板。
- 前記電極は、前記凹部内から連続して前記基板の上面にも位置していることを特徴とする請求項1または2に記載の電子素子実装用基板。
- 前記電極は、前記凹部内から連続して前記基板の下面にも位置していることを特徴とする請求項1〜3のいずれか1つに記載の電子素子実装用基板。
- 前記基板は、前記複数の層の積層方向に貫通している貫通孔を有していることを特徴とする請求項1〜4のいずれか1つに記載の電子素子実装用基板。
- 請求項1〜5のいずれか1つに記載の電子素子実装用基板と、
前記電子素子実装用基板に実装された電子素子とを備えていることを特徴とする電子装置。 - 請求項6に記載の電子装置と、
前記電子装置の上面または電子装置を囲んで位置した筐体とを備えていることを特徴とする電子モジュール。
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