JP2018504020A5 - - Google Patents
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- Publication number
- JP2018504020A5 JP2018504020A5 JP2017530262A JP2017530262A JP2018504020A5 JP 2018504020 A5 JP2018504020 A5 JP 2018504020A5 JP 2017530262 A JP2017530262 A JP 2017530262A JP 2017530262 A JP2017530262 A JP 2017530262A JP 2018504020 A5 JP2018504020 A5 JP 2018504020A5
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- digital signal
- coupled
- signal
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201462089497P | 2014-12-09 | 2014-12-09 | |
| US62/089,497 | 2014-12-09 | ||
| US14/640,672 | 2015-03-06 | ||
| US14/640,672 US9490784B2 (en) | 2014-12-09 | 2015-03-06 | Apparatus and method for generating quadrupled reference clock from single ended crystal oscillator |
| PCT/US2015/063815 WO2016094196A1 (en) | 2014-12-09 | 2015-12-03 | Apparatus and method for generating quadrupled reference clock from single-ended crystal oscillator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2018504020A JP2018504020A (ja) | 2018-02-08 |
| JP2018504020A5 true JP2018504020A5 (enExample) | 2018-12-20 |
Family
ID=56095255
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2017530262A Pending JP2018504020A (ja) | 2014-12-09 | 2015-12-03 | シングルエンドクリスタル発振器から４倍の基準クロックを生成するための装置および方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US9490784B2 (enExample) |
| EP (1) | EP3231089A1 (enExample) |
| JP (1) | JP2018504020A (enExample) |
| CN (1) | CN107005230B (enExample) |
| WO (1) | WO2016094196A1 (enExample) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107991553B (zh) * | 2017-11-21 | 2019-12-31 | 中国电子科技集团公司第四十一研究所 | 一种矢量网络分析仪时钟系统及其优化方法 |
| US10749473B2 (en) * | 2017-12-20 | 2020-08-18 | Globalfoundries Inc. | Methods, apparatus, and system for a frequency doubler for a millimeter wave device |
| IT201800007998A1 (it) * | 2018-08-09 | 2020-02-09 | Magaldi Power Spa | Dispositivo, impianto e metodo per l'accumulo e il trasferimento di energia termica di origine solare |
| KR20220154482A (ko) | 2021-05-13 | 2022-11-22 | 삼성전자주식회사 | 클록 생성 회로 및 이를 포함하는 무선 통신 장치 |
Family Cites Families (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62179213A (ja) * | 1986-02-03 | 1987-08-06 | Matsushita Electric Ind Co Ltd | 逓倍回路 |
| JPH0268523U (enExample) * | 1988-11-11 | 1990-05-24 | ||
| JPH0786882A (ja) * | 1993-09-17 | 1995-03-31 | Mitsubishi Electric Corp | 逓倍回路 |
| US5828250A (en) * | 1994-09-06 | 1998-10-27 | Intel Corporation | Differential delay line clock generator with feedback phase control |
| JP3332634B2 (ja) * | 1995-01-30 | 2002-10-07 | 三洋電機株式会社 | デューティ調整装置 |
| US5963071A (en) * | 1998-01-22 | 1999-10-05 | Nanoamp Solutions, Inc. | Frequency doubler with adjustable duty cycle |
| JP3495311B2 (ja) | 2000-03-24 | 2004-02-09 | Ｎｅｃエレクトロニクス株式会社 | クロック制御回路 |
| US6480045B2 (en) * | 2001-01-05 | 2002-11-12 | Thomson Licensing S.A. | Digital frequency multiplier |
| KR20040034985A (ko) * | 2002-10-18 | 2004-04-29 | 엘지전자 주식회사 | 클럭신호 생성회로 |
| JP3569754B2 (ja) * | 2002-11-07 | 2004-09-29 | 沖電気工業株式会社 | クロックパルス生成回路 |
| KR100493046B1 (ko) * | 2003-02-04 | 2005-06-07 | 삼성전자주식회사 | 클럭의 듀티 사이클을 조정할 수 있는 주파수 체배기 및체배방법 |
| TW200427224A (en) * | 2003-05-21 | 2004-12-01 | Myson Century Inc | Clock multiplier |
| US6967508B2 (en) * | 2004-03-04 | 2005-11-22 | Texas Instruments Incorporated | Compact frequency doubler/multiplier circuitry |
| US7865756B2 (en) | 2007-03-12 | 2011-01-04 | Mosaid Technologies Incorporated | Methods and apparatus for clock signal synchronization in a configuration of series-connected semiconductor devices |
| US7786780B2 (en) | 2007-07-10 | 2010-08-31 | Jennic Limited | Clock doubler circuit and method |
| CN101378259A (zh) * | 2007-08-31 | 2009-03-04 | 锐迪科微电子（上海）有限公司 | 相位选择可编程分频器 |
| US7898309B1 (en) | 2009-05-14 | 2011-03-01 | Atheros Communications, Inc. | Analog duty cycle correction loop for clocks |
| CN102664608B (zh) * | 2010-12-28 | 2015-03-11 | 博通集成电路（上海）有限公司 | 频率倍增器及频率倍增的方法 |
| CN102361453B (zh) | 2011-08-15 | 2013-01-23 | 中国电子科技集团公司第二十四研究所 | 用于锁相环的高速占空比调节和双端转单端电路 |
| TWI448081B (zh) | 2012-01-20 | 2014-08-01 | Nat Univ Chung Cheng | All-digital clock correction circuit and method thereof |
| US8629708B2 (en) | 2012-01-22 | 2014-01-14 | International Business Machines Corporation | High conversion gain high suppression balanced cascode frequency quadrupler |
| US8736329B1 (en) | 2013-02-06 | 2014-05-27 | Qualcomm Incorporated | Systems and methods for providing duty cycle correction |
| EP2765474B1 (en) | 2013-02-12 | 2015-05-20 | Nxp B.V. | Clock buffer |
| US8988121B2 (en) * | 2013-05-20 | 2015-03-24 | Qualcomm Incoporated | Method and apparatus for generating a reference signal for a fractional-N frequency synthesizer |
| JP6465270B2 (ja) * | 2014-07-23 | 2019-02-06 | セイコーエプソン株式会社 | 周波数逓倍回路、電子機器及び移動体 |
| US20160099729A1 (en) * | 2014-10-02 | 2016-04-07 | Qualcomm Incorporated | Apparatus and method for quadrupling frequency of reference clock |
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2015
- 2015-03-06 US US14/640,672 patent/US9490784B2/en not_active Expired - Fee Related
- 2015-12-03 JP JP2017530262A patent/JP2018504020A/ja active Pending
- 2015-12-03 EP EP15813214.2A patent/EP3231089A1/en not_active Withdrawn
- 2015-12-03 WO PCT/US2015/063815 patent/WO2016094196A1/en not_active Ceased
- 2015-12-03 CN CN201580066418.5A patent/CN107005230B/zh not_active Expired - Fee Related