JP2017509217A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2017509217A5 JP2017509217A5 JP2016548263A JP2016548263A JP2017509217A5 JP 2017509217 A5 JP2017509217 A5 JP 2017509217A5 JP 2016548263 A JP2016548263 A JP 2016548263A JP 2016548263 A JP2016548263 A JP 2016548263A JP 2017509217 A5 JP2017509217 A5 JP 2017509217A5
- Authority
- JP
- Japan
- Prior art keywords
- input
- output
- signal
- dll
- logic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000003111 delayed effect Effects 0.000 claims description 24
- 238000001514 detection method Methods 0.000 claims description 11
- 230000000630 rising effect Effects 0.000 claims description 5
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201461932088P | 2014-01-27 | 2014-01-27 | |
| US61/932,088 | 2014-01-27 | ||
| US14/268,120 US9191185B2 (en) | 2014-01-27 | 2014-05-02 | Differential bang-bang phase detector using standard digital cells |
| US14/268,120 | 2014-05-02 | ||
| PCT/US2015/010086 WO2015112321A1 (en) | 2014-01-27 | 2015-01-05 | Differential bang-bang phase detector using standard digital cells |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2017509217A JP2017509217A (ja) | 2017-03-30 |
| JP2017509217A5 true JP2017509217A5 (enExample) | 2018-01-25 |
| JP6526024B2 JP6526024B2 (ja) | 2019-06-05 |
Family
ID=53680124
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2016548263A Active JP6526024B2 (ja) | 2014-01-27 | 2015-01-05 | 標準的なデジタルセルを使用する差動バンバン位相検出器 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US9191185B2 (enExample) |
| EP (1) | EP3100358B1 (enExample) |
| JP (1) | JP6526024B2 (enExample) |
| KR (1) | KR20160113632A (enExample) |
| CN (1) | CN105934884B (enExample) |
| WO (1) | WO2015112321A1 (enExample) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9641182B2 (en) * | 2014-01-31 | 2017-05-02 | Nvidia Corporation | System and method for dynamic frequency estimation for a spread-spectrum digital phase-locked loop |
| US9755653B2 (en) * | 2014-11-05 | 2017-09-05 | Mediatek Inc. | Phase detector |
| US9973195B2 (en) * | 2015-04-08 | 2018-05-15 | Infineon Technologies Ag | Local phase detection in realigned oscillator |
| US9998128B2 (en) | 2015-04-08 | 2018-06-12 | Infineon Technologies Ag | Frequency synthesizer with injection locked oscillator |
| US9985618B2 (en) | 2015-12-23 | 2018-05-29 | Qualcomm Incorporated | Digital duty cycle correction for frequency multiplier |
| CN107528583B (zh) * | 2016-06-21 | 2022-04-19 | 马维尔亚洲私人有限公司 | 使用采样时间至数字转换器的倍频延迟锁定环路 |
| US10250375B2 (en) * | 2016-09-22 | 2019-04-02 | Qualcomm Incorporated | Clock synchronization |
| CN107528584A (zh) * | 2017-07-19 | 2017-12-29 | 成都华微电子科技有限公司 | 复用延迟线的高精度数字延时锁相环 |
| RU2665241C1 (ru) * | 2017-10-13 | 2018-08-28 | Геннадий Сендерович Брайловский | Способ подстройки частоты и фазовый детектор |
| CN107707233B (zh) * | 2017-11-03 | 2020-09-01 | 中国电子科技集团公司第五十四研究所 | 一种防止瞬间掉电引起二次复位的复位电路 |
| US10541691B1 (en) | 2019-02-25 | 2020-01-21 | International Business Machines Corporation | Bang-bang phase detectors |
| US11568948B2 (en) * | 2021-02-12 | 2023-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory circuit and method of operating same |
| US12323160B2 (en) * | 2021-05-19 | 2025-06-03 | Cirrus Logic Inc. | Filters |
| US12476641B2 (en) * | 2022-07-14 | 2025-11-18 | Samsung Electronics Co., Ltd. | Clock selection method for multiplying delay locked loop |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5355037A (en) * | 1992-06-15 | 1994-10-11 | Texas Instruments Incorporated | High performance digital phase locked loop |
| JPH11110065A (ja) * | 1997-10-03 | 1999-04-23 | Mitsubishi Electric Corp | 内部クロック信号発生回路 |
| US6952431B1 (en) | 1999-10-28 | 2005-10-04 | Rambus Inc. | Clock multiplying delay-locked loop for data communications |
| US6674772B1 (en) * | 1999-10-28 | 2004-01-06 | Velio Communicaitons, Inc. | Data communications circuit with multi-stage multiplexing |
| US6633184B2 (en) * | 2000-05-19 | 2003-10-14 | Yazaki Corporation | Phase comparator and synchronizing signal extracting device |
| US6674309B1 (en) | 2002-11-12 | 2004-01-06 | Analog Devices, Inc. | Differential time sampling circuit |
| KR100552469B1 (ko) * | 2003-01-13 | 2006-02-15 | 삼성전자주식회사 | 위상차 제거기능을 갖는 트랙에러검출장치 및 그의위상차제거방법 |
| US7190201B2 (en) | 2005-02-03 | 2007-03-13 | Mosaid Technologies, Inc. | Method and apparatus for initializing a delay locked loop |
| CN101221894B (zh) * | 2007-01-10 | 2010-10-06 | 北京北方微电子基地设备工艺研究中心有限责任公司 | 一种射频匹配器的传感器的鉴相装置和方法 |
| JP2009159038A (ja) * | 2007-12-25 | 2009-07-16 | Hitachi Ltd | Pll回路 |
| JP5034938B2 (ja) * | 2007-12-28 | 2012-09-26 | 富士通株式会社 | 位相比較器及び測定装置 |
| CN102047133A (zh) | 2008-05-29 | 2011-05-04 | Nxp股份有限公司 | 用于周期抖动测量的延迟锁定环 |
| CN101776933B (zh) * | 2009-12-25 | 2012-05-30 | 福建星网锐捷网络有限公司 | 一种冷热启动的判定电路、装置及交换机 |
| KR101153219B1 (ko) * | 2010-03-18 | 2012-06-07 | 매그나칩 반도체 유한회사 | 디밍 신호를 이용한 dc-dc 컨버터용 pwm 신호 발생회로 및 방법과 이를 구비한 백라이트용 led 구동 회로 |
| US8638145B2 (en) | 2011-12-30 | 2014-01-28 | Advanced Micro Devices, Inc. | Method for locking a delay locked loop |
| US8536915B1 (en) | 2012-07-02 | 2013-09-17 | Qualcomm Incorporated | Low-noise and low-reference spur frequency multiplying delay lock-loop |
| US8686776B2 (en) | 2012-07-24 | 2014-04-01 | International Business Machines Corporation | Phase rotator based on voltage referencing |
-
2014
- 2014-05-02 US US14/268,120 patent/US9191185B2/en active Active
-
2015
- 2015-01-05 WO PCT/US2015/010086 patent/WO2015112321A1/en not_active Ceased
- 2015-01-05 KR KR1020167022601A patent/KR20160113632A/ko not_active Ceased
- 2015-01-05 CN CN201580005792.4A patent/CN105934884B/zh active Active
- 2015-01-05 JP JP2016548263A patent/JP6526024B2/ja active Active
- 2015-01-05 EP EP15701056.2A patent/EP3100358B1/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2017509217A5 (enExample) | ||
| JP2020513539A5 (enExample) | ||
| JP2017508319A5 (enExample) | ||
| EP4376005A3 (en) | Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal | |
| GB2525115A (en) | Apparatus and method for communication between downhole components | |
| JP2016517215A5 (enExample) | ||
| WO2012021511A3 (en) | High-speed frequency divider and phase locked loop using same | |
| MX350767B (es) | Sistema y método para evitar la polarización de cc en un receptor homodino. | |
| CN102361456A (zh) | 一种时钟相位对齐调整电路 | |
| US9722590B1 (en) | Skew adjustment circuit, semiconductor device, and skew calibration method | |
| WO2013188272A3 (en) | Optimizing power in a memory device | |
| CN103684447B (zh) | 时钟数据恢复电路及数据锁定的判断方法 | |
| GB201112634D0 (en) | Spreading a clock signal | |
| CN103516355A (zh) | 延迟控制电路和包括延迟控制电路的时钟发生电路 | |
| US8036318B2 (en) | Clock and data recovery circuit | |
| PH12017502159A1 (en) | Frequency divider, phase-locked loop, transceiver, radio station and method of frequency dividing | |
| JP4772733B2 (ja) | Dll回路 | |
| CN104242921A (zh) | 一种高频延迟锁相环及其时钟处理方法 | |
| JP2008084303A5 (enExample) | ||
| CN105610413B (zh) | 一种占空比矫正电路及增大输入时钟范围的方法 | |
| TWI427999B (zh) | 時脈產生電路、收發器以及其相關方法 | |
| CN104253610A (zh) | 一种延迟锁相环防止错锁的电路及方法 | |
| CN104917497B (zh) | 一种基于逻辑延时锁定的抗干扰电路及方法 | |
| KR20180119931A (ko) | 도플러신호 구현이 가능한 모의고도 발생장치 및 모의고도 발생방법 | |
| CN104283550A (zh) | 一种延迟锁相环和占空比矫正电路 |