JP6526024B2 - 標準的なデジタルセルを使用する差動バンバン位相検出器 - Google Patents

標準的なデジタルセルを使用する差動バンバン位相検出器 Download PDF

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Publication number
JP6526024B2
JP6526024B2 JP2016548263A JP2016548263A JP6526024B2 JP 6526024 B2 JP6526024 B2 JP 6526024B2 JP 2016548263 A JP2016548263 A JP 2016548263A JP 2016548263 A JP2016548263 A JP 2016548263A JP 6526024 B2 JP6526024 B2 JP 6526024B2
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Japan
Prior art keywords
input
signal
output
logic
latch
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JP2016548263A
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Japanese (ja)
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JP2017509217A (ja
JP2017509217A5 (enExample
Inventor
チェン、ジア−イ
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Qualcomm Inc
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Qualcomm Inc
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Publication of JP2017509217A5 publication Critical patent/JP2017509217A5/ja
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H04L7/0041—Delay of data signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0818—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter comprising coarse and fine delay or phase-shifting means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0045—Correction by a latch cascade
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0332—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with an integrator-detector

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Manipulation Of Pulses (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Pulse Circuits (AREA)
JP2016548263A 2014-01-27 2015-01-05 標準的なデジタルセルを使用する差動バンバン位相検出器 Active JP6526024B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201461932088P 2014-01-27 2014-01-27
US61/932,088 2014-01-27
US14/268,120 US9191185B2 (en) 2014-01-27 2014-05-02 Differential bang-bang phase detector using standard digital cells
US14/268,120 2014-05-02
PCT/US2015/010086 WO2015112321A1 (en) 2014-01-27 2015-01-05 Differential bang-bang phase detector using standard digital cells

Publications (3)

Publication Number Publication Date
JP2017509217A JP2017509217A (ja) 2017-03-30
JP2017509217A5 JP2017509217A5 (enExample) 2018-01-25
JP6526024B2 true JP6526024B2 (ja) 2019-06-05

Family

ID=53680124

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016548263A Active JP6526024B2 (ja) 2014-01-27 2015-01-05 標準的なデジタルセルを使用する差動バンバン位相検出器

Country Status (6)

Country Link
US (1) US9191185B2 (enExample)
EP (1) EP3100358B1 (enExample)
JP (1) JP6526024B2 (enExample)
KR (1) KR20160113632A (enExample)
CN (1) CN105934884B (enExample)
WO (1) WO2015112321A1 (enExample)

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US9641182B2 (en) * 2014-01-31 2017-05-02 Nvidia Corporation System and method for dynamic frequency estimation for a spread-spectrum digital phase-locked loop
US9755653B2 (en) * 2014-11-05 2017-09-05 Mediatek Inc. Phase detector
US9973195B2 (en) * 2015-04-08 2018-05-15 Infineon Technologies Ag Local phase detection in realigned oscillator
US9998128B2 (en) 2015-04-08 2018-06-12 Infineon Technologies Ag Frequency synthesizer with injection locked oscillator
US9985618B2 (en) 2015-12-23 2018-05-29 Qualcomm Incorporated Digital duty cycle correction for frequency multiplier
CN107528583B (zh) * 2016-06-21 2022-04-19 马维尔亚洲私人有限公司 使用采样时间至数字转换器的倍频延迟锁定环路
US10250375B2 (en) * 2016-09-22 2019-04-02 Qualcomm Incorporated Clock synchronization
CN107528584A (zh) * 2017-07-19 2017-12-29 成都华微电子科技有限公司 复用延迟线的高精度数字延时锁相环
RU2665241C1 (ru) * 2017-10-13 2018-08-28 Геннадий Сендерович Брайловский Способ подстройки частоты и фазовый детектор
CN107707233B (zh) * 2017-11-03 2020-09-01 中国电子科技集团公司第五十四研究所 一种防止瞬间掉电引起二次复位的复位电路
US10541691B1 (en) 2019-02-25 2020-01-21 International Business Machines Corporation Bang-bang phase detectors
US11568948B2 (en) * 2021-02-12 2023-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Memory circuit and method of operating same
US12323160B2 (en) * 2021-05-19 2025-06-03 Cirrus Logic Inc. Filters
US12476641B2 (en) * 2022-07-14 2025-11-18 Samsung Electronics Co., Ltd. Clock selection method for multiplying delay locked loop

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US5355037A (en) * 1992-06-15 1994-10-11 Texas Instruments Incorporated High performance digital phase locked loop
JPH11110065A (ja) * 1997-10-03 1999-04-23 Mitsubishi Electric Corp 内部クロック信号発生回路
US6952431B1 (en) 1999-10-28 2005-10-04 Rambus Inc. Clock multiplying delay-locked loop for data communications
US6674772B1 (en) * 1999-10-28 2004-01-06 Velio Communicaitons, Inc. Data communications circuit with multi-stage multiplexing
US6633184B2 (en) * 2000-05-19 2003-10-14 Yazaki Corporation Phase comparator and synchronizing signal extracting device
US6674309B1 (en) 2002-11-12 2004-01-06 Analog Devices, Inc. Differential time sampling circuit
KR100552469B1 (ko) * 2003-01-13 2006-02-15 삼성전자주식회사 위상차 제거기능을 갖는 트랙에러검출장치 및 그의위상차제거방법
US7190201B2 (en) 2005-02-03 2007-03-13 Mosaid Technologies, Inc. Method and apparatus for initializing a delay locked loop
CN101221894B (zh) * 2007-01-10 2010-10-06 北京北方微电子基地设备工艺研究中心有限责任公司 一种射频匹配器的传感器的鉴相装置和方法
JP2009159038A (ja) * 2007-12-25 2009-07-16 Hitachi Ltd Ｐｌｌ回路
JP5034938B2 (ja) * 2007-12-28 2012-09-26 富士通株式会社 位相比較器及び測定装置
CN102047133A (zh) 2008-05-29 2011-05-04 Nxp股份有限公司 用于周期抖动测量的延迟锁定环
CN101776933B (zh) * 2009-12-25 2012-05-30 福建星网锐捷网络有限公司 一种冷热启动的判定电路、装置及交换机
KR101153219B1 (ko) * 2010-03-18 2012-06-07 매그나칩 반도체 유한회사 디밍 신호를 이용한 ｄｃ-ｄｃ 컨버터용 ｐｗｍ 신호 발생회로 및 방법과 이를 구비한 백라이트용 ｌｅｄ 구동 회로
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Also Published As

Publication number Publication date
CN105934884B (zh) 2019-01-08
EP3100358B1 (en) 2019-07-24
JP2017509217A (ja) 2017-03-30
CN105934884A (zh) 2016-09-07
EP3100358A1 (en) 2016-12-07
WO2015112321A1 (en) 2015-07-30
US9191185B2 (en) 2015-11-17
KR20160113632A (ko) 2016-09-30
US20150215110A1 (en) 2015-07-30

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