US8629708B2 - High conversion gain high suppression balanced cascode frequency quadrupler - Google Patents
High conversion gain high suppression balanced cascode frequency quadrupler Download PDFInfo
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- US8629708B2 US8629708B2 US13/355,537 US201213355537A US8629708B2 US 8629708 B2 US8629708 B2 US 8629708B2 US 201213355537 A US201213355537 A US 201213355537A US 8629708 B2 US8629708 B2 US 8629708B2
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B19/00—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source
- H03B19/06—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source by means of discharge device or semiconductor device with more than two electrodes
- H03B19/14—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source by means of discharge device or semiconductor device with more than two electrodes by means of a semiconductor device
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- the present invention relates to the field of high speed circuit design, and more particularly relates to a high conversion gain, high suppression balanced cascode frequency quadrupler.
- a frequency multiplier is an electronic circuit that generates an output signal whose output frequency is a harmonic of its input frequency.
- Frequency multipliers generally consist of a nonlinear circuit that distorts the input signal and consequently generates harmonics of the input signal.
- a subsequent bandpass filter selects the desired harmonic frequency and removes the unwanted fundamental and other harmonics from the output.
- Frequency multipliers are often used in frequency synthesizers and communications circuits. It can be more economic to develop a lower frequency signal with lower power and less expensive devices, and then use a frequency multiplier chain to generate an output frequency in the microwave or millimeter wave range.
- the millimeter wave (mmWave) frequency range has recently become attractive for many applications, such as wireless communications, automotive based radar and imaging applications, etc.
- the implementation of low phase noise oscillators at such high frequencies is not trivial.
- Some high frequency oscillator applications incorporate a frequency multiplier which is an important component in many of these systems.
- a frequency quadrupler circuit comprising a first amplifier stage coupled to a differential input signal and operative to generate a plurality of harmonics therefrom, a second amplifier stage coupled to said first amplifier stage and operative to generate an amplified output signal from the output of said first amplifier stage, and a notch filter coupled to the input of said second amplifier stage and operative to suppress second harmonics generated by said first amplifier stage.
- a frequency quadrupler circuit comprising a common emitter amplifier stage coupled to a differential input signal and operative to generate a plurality of harmonics therefrom, a common base amplifier stage coupled to said common emitter amplifier stage, and a notch filter coupled to the input of said common base amplifier stage and operative to suppress a second harmonic generated by said common emitter amplifier stage.
- a method of frequency quadrupling comprising providing a common emitter amplifier stage for generating a plurality of harmonics from a differential input signal, providing a common base amplifier stage for generating an amplified output signal from said common emitter amplifier stage, and providing a notch filter operative to filter out second harmonics from the output of said common emitter amplifier stage before being input to said common base amplifier stage.
- a frequency quadrupler circuit comprising a common source amplifier stage coupled to a differential input signal and operative to generate a plurality of harmonics therefrom, a common gate amplifier stage coupled to said common source amplifier stage, and a notch filter coupled to the input of said common gate amplifier stage and operative to suppress a second harmonic generated by said common source amplifier stage.
- FIG. 1 is a block diagram illustrating an example balanced cascade frequency quadrupler constructed in accordance with the present invention
- FIG. 2 is a graph illustrating 4 th harmonic conversion gain versus fundamental input power
- FIG. 3 is a graph illustrating 4 th harmonic output power versus fundamental input power.
- a local oscillator based high frequency source uses a high spectral purity voltage controlled oscillator (VCO) at lower frequency bands, the output of which is followed by a frequency multiplier.
- VCO voltage controlled oscillator
- the output of Ku-band or K-band VCOs need to be quadrupled in order to generate a local oscillator (LO) signal in the 60-77 GHz frequency range.
- This scheme requires several filtering and amplifying stages, in order to achieve high 4 th harmonic conversion gain and high suppression for the other harmonics.
- This scheme results in an increase in chip area and power consumptions.
- the problem may aggravate since increasing the number of stages reduces the design robustness to temperature, supply voltage and process variation.
- FIG. 1 A block diagram illustrating an example balanced cascade frequency quadrupler constructed in accordance with the present invention is shown in FIG. 1 .
- the frequency quadrupler circuit generally referenced 10 , comprises transistors Q 1 , Q 2 , Q 3 , Q 4 , capacitors C 1 , C 2 , C 3 , C 4 , C 5 , resistors R 1 , R 2 , and inductances L 1 , L 2 , L 3 .
- the frequency quadrupler uses a balanced topology to increase broadband odd harmonic suppression, while a cascode configuration is used to improve the multiplier frequency response.
- the cascode design also enables a notch filter to be placed between the common emitter (CE) and common base (CB) stages to reduce the 2 nd harmonics generated and thereby increase the 4 th harmonic power, generation efficiency and conversion gain.
- the frequency quadrupler of the present invention comprises a balanced topology which increases broadband odd harmonic suppression.
- the frequency quadrupler is constructed in a cascode configuration.
- the cascode is a two-stage amplifier composed of a transconductance amplifier followed by a current buffer.
- the cascode configuration is constructed with common emitter (CE) and common base (CB) stages which further improves the multiplier frequency response.
- CE common emitter
- CB common base
- the cascode configuration enables a notch filter to be placed between the common emitter and common base stages to reduce 2 nd harmonic generation and thereby increase 4 th harmonic power output generation, output efficiency and conversion gain.
- capacitors are placed at the input of the common emitter stage, which in conjunction with the parasitic base wire inductance, form a notch filter to short (filter out) the 4 th harmonic.
- the same balanced cascode circuit can be implemented using MOSFET devices, where Q 1 and Q 2 serve as a common source (CS) stage and Q 3 and Q 4 serve as a common gate (CG) stage.
- CS common source
- CG common gate
- frequency quadrupler is not limited to the example described herein but may be constructed to have other configurations depending on the particular implementation.
- an unbalanced cascode frequency quadrupler can be constructed where the input is a single ended signal rather than differential.
- the differential input signals (+input 12 , ⁇ input 14 ) with fundamental frequency f 0 are fed into the base of common emitter transistors Q 1 and Q 2 , biased by a band-gap reference circuit (VB 1 ) for maximum f T operation point.
- the emitters of Q 1 , Q 2 are tied to ground.
- a balanced topology is used to increase broadband odd harmonic suppression, while a cascode configuration with Q 3 and Q 4 common base stages is used to improve the multiplier frequency response.
- the base of both Q 3 and A 4 are tied to a band-gap reference circuit (VB 2 ).
- the load a tank circuit
- L 3 e.g., transmission line inductance
- a notch filter is placed between the common emitter stage (Q 1 , Q 2 ) and the common base stage (Q 3 , Q 4 ) to filter out/suppress 2 nd harmonic generation and thereby increase the 4 th harmonic power.
- Each notch filter comprises a series combination of capacitor and inductance placed between the common emitter and common base stages and ground.
- a notch filter comprising the series combination of capacitor C 1 and inductance L 1 is placed between Q 1 , Q 3 and ground.
- a second notch filter comprising the series combination of capacitor C 2 and inductance L 2 is placed between Q 2 , Q 4 and ground.
- the output 16 of the cascode configuration is the 4 th harmonic (4f 0 ) of the input signal.
- the notch filters are tuned to 1 ⁇ 4 wavelength ( ⁇ ) (i.e. the 2 nd harmonic).
- ⁇ 1 ⁇ 4 wavelength
- the filtering out of the 2 nd harmonic from the harmonics generated by the common emitter amplifier stage (Q 1 , Q 2 ) occurs before the second amplification performed by the common base stage (Q 3 , Q 4 )
- capacitors C 4 and C 5 are placed in the input of the common emitter stage. Capacitors C 4 and C 5 in combination with the parasitic base wire inductances of Q 1 and Q 2 form a notch filter to short the 4 th harmonic.
- the equation can be linearized and only the first two terms are considered, i.e. the DC ‘a0’ term and the linear component ‘a1’ term. Note that this linearization is only valid if V in is small enough.
- V in is not sufficiently small, the other terms cannot be ignored and must be considered as well.
- V in is a sine wave, the output will comprise the fundamental harmonic from the a1*V in term, the second harmonic from the a2*V in ⁇ 2 term, and so on.
- the 4 th harmonic at the input is generated from the parasitic capacitance between the collector (i.e. common emitter output) and base (i.e. common emitter input) of the Bipolar Junction Transistors (BJT) transistors Q 1 and Q 2 .
- This parasitic capacitance connects the common emitter stage output to input, and therefore the “generated” 4th harm can return to the input thought this capacitor
- FIG. 2 A graph illustrating 4 th harmonic conversion gain versus fundamental input power is shown in FIG. 2 .
- the graph shows the 4 th harmonic conversion gain at the output of the quadrupler as a function of input power for an input frequency (f 0 ) of 16 GHz with an input power from ⁇ 20 dBm to +10 dBm.
- the quadrupler shows 4 th harmonic conversion loss of approximately 8-10 dB at an input power level of 0 dBm.
- the 2 nd harmonic is suppressed by 20 dB
- the frequency quadrupler in order to produce a differential LO signal required by some mixer topologies, is cascaded with a lumped balun and a differential amplifying stage both tuned to the 4 th harmonic frequency range to generate a balanced LO signal with +2 to +5 dBm power and in order to further suppress the 2 nd harmonic.
- FIG. 3 A graph illustrating 4 th harmonic output power versus fundamental input power is shown in FIG. 3 .
- the 4 th harmonic output power at the output of the frequency quadrupler is shown as a function of input power at a fundamental frequency of 16 GHz.
- the graph shows an output power of ⁇ 6 dBm at saturation of the 4 th harmonic.
- the frequency quadrupler of the present invention employs a high suppression, balanced cascode topology, implemented in SiGe BiCMOS technology. Such an implementation exhibits a high conversion gain and high suppression for the 60-77 GHz frequency range with a measured value of quadrupler conversion loss of approximately 8 dB.
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Description
I out=10*exp(V in /kT) (1)
The exponent can be expanded using the well-known Taylor series to
I out =a0+a1*V in +a2*V in^2+a3*V in^3+a4*V in^4+ . . . (2)
Typically, in analog circuits, the equation can be linearized and only the first two terms are considered, i.e. the DC ‘a0’ term and the linear component ‘a1’ term. Note that this linearization is only valid if Vin is small enough. If Vin is not sufficiently small, the other terms cannot be ignored and must be considered as well. Thus, if Vin is a sine wave, the output will comprise the fundamental harmonic from the a1*Vin term, the second harmonic from the a2*Vin^2 term, and so on.
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US13/355,537 US8629708B2 (en) | 2012-01-22 | 2012-01-22 | High conversion gain high suppression balanced cascode frequency quadrupler |
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US9490784B2 (en) | 2014-12-09 | 2016-11-08 | Qualcomm Incorporated | Apparatus and method for generating quadrupled reference clock from single ended crystal oscillator |
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US20150056940A1 (en) * | 2013-08-23 | 2015-02-26 | Qualcomm Incorporated | Harmonic trap for common gate amplifier |
US20150072615A1 (en) * | 2013-09-06 | 2015-03-12 | Qualcomm Incorporated | Systems and methods for reducing transmission interference with a parasitic loop |
KR102150278B1 (en) * | 2014-02-12 | 2020-09-01 | 한국전자통신연구원 | High frequency transceiver |
TWI639328B (en) * | 2017-03-03 | 2018-10-21 | 國立暨南國際大學 | Digital modulation device and digital modulation frequency multiplier |
US10855225B1 (en) * | 2019-12-23 | 2020-12-01 | Qualcomm Incorporated | Radio frequency low power differential frequency multiplier |
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US5815014A (en) * | 1996-06-28 | 1998-09-29 | The Whitaker Corporation | Transistor based frequency multiplier |
US20060145737A1 (en) * | 2005-01-06 | 2006-07-06 | Mitsubishi Denki Kabushiki Kaisha | Current-reuse-type frequency multiplier |
US20100158084A1 (en) | 2007-05-25 | 2010-06-24 | Voinigescu Sorin P | High frequency system on chip transceiver |
US8237472B2 (en) * | 2010-01-29 | 2012-08-07 | National Chiao Tung University | Frequency multiplier device and method thereof |
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2012
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US5815014A (en) * | 1996-06-28 | 1998-09-29 | The Whitaker Corporation | Transistor based frequency multiplier |
US20060145737A1 (en) * | 2005-01-06 | 2006-07-06 | Mitsubishi Denki Kabushiki Kaisha | Current-reuse-type frequency multiplier |
US20100158084A1 (en) | 2007-05-25 | 2010-06-24 | Voinigescu Sorin P | High frequency system on chip transceiver |
US8237472B2 (en) * | 2010-01-29 | 2012-08-07 | National Chiao Tung University | Frequency multiplier device and method thereof |
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Campos-Roca, et al., "Coplanar pHEMT MMIC frequency multipliers for 76-GHz automotive radar", Microwave and Guided Wave Letters, IEEE, vol. 9 Issue: 6, pp. 242-244, Jun. 1999. |
Hung et al, "High-Power High-Efficiency SiGe Ku- and Ka-Band Balanced Frequency Doublers" IEEE Trans. Microwave Theory & Tech., vol. 53, No. 2, pp. 754-761, Feb. 2005. |
Kuo, et al., "A 52-75 GHz frequency quadrupler in 0.25-mum SiGe BiCMOS process", Microwave Integrated Circuits Conference (EuMIC), 2010 European, pp. 365-368, Sep. 2010. |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9490784B2 (en) | 2014-12-09 | 2016-11-08 | Qualcomm Incorporated | Apparatus and method for generating quadrupled reference clock from single ended crystal oscillator |
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