JP2001274629A - Frequency multiplier and transmitter-receiver using it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a small-sized frequency multiplier with low power consumption that is used for a microwave band such as millimeter waves. SOLUTION: An output transmission line for a microwave transistor(TR) that applies nonlinear conversion to a microwave input signal is provided with a 3rd harmonic wave suppression circuit in addition to a fundamental wave suppression circuit and a 2nd harmonic wave suppression circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication device,
More particularly, the present invention relates to a frequency multiplier configured using a microwave transistor for nonlinearly converting a microwave input signal and a transmitting / receiving apparatus using the same. Things.

[0002]

2. Description of the Related Art In recent years, in order to realize portable and low-cost wireless communication, a local oscillator in the transmission / reception apparatus tends to be configured using a low-noise synthesizer. Also,
The local oscillator tends to be configured using a frequency multiplier as the frequency of a radio circuit is changed to a quasi-millimeter wave or a millimeter wave.

Conventionally, a local oscillator in a microwave band or a millimeter wave band is composed of a signal source such as a microwave band phase-locked oscillator (PL0) and a frequency doubler from the viewpoint of reduction in manufacturing cost and labor. The frequency f0 of the microwave input signal from the signal source is multiplied by the frequency multiplier to generate a desired high frequency.

FIG. 11 shows a basic configuration of the conventional frequency multiplier. In FIG. 11, an input signal f0 is input to a nonlinear element 11 such as a microwave transistor through an input matching circuit 10. The microwave input signal having the frequency f0 in the millimeter wave band input to the input terminal 1 is passed through the nonlinear element 11 via the input matching circuit 10 to generate a distortion component, that is, a fundamental wave of the microwave input signal. A signal including a frequency component that is an integral multiple of a certain first frequency f0 is generated. The signal output from the nonlinear element 11 is reduced in frequency by the power of the fundamental wave component by a band stop circuit 12 composed of a band-pass filter and a fundamental wave trap circuit, and the frequency component nf0 ( ..), and the second frequency signal is output to the output terminal 2 via the output matching circuit 13.

In the frequency multiplier having the above-described structure, the frequency conversion efficiency generally decreases as the number of multipliers increases, and the output of the even-numbered multiple-wave is reduced due to the conversion characteristics of the nonlinear element 11. The frequency multiplication factor by one nonlinear element is generally set to a maximum of four times because the conversion efficiency is better than the output.

FIG. 12 shows an example of a conventional multistage frequency octupler 4 used for a local oscillator in a microwave band or a millimeter wave band. This conventional frequency doubling device 4 has 3
The frequency doublers 5, 6 and 7 are connected in cascade. The microwave input signal output from the phase-locked oscillator (PL0) 23 doubles the frequency of the input signal each time it passes through each frequency doubler, so that the frequency doubler 5 cascaded in three stages , 6 and 7, a signal containing an eighth harmonic component of the fundamental wave f0 of the input signal is output, and an eighth harmonic signal is taken out to the output terminal 2 via the band pass filter (BPF) 8. . In the above-mentioned local oscillator, the frequency doubler, in principle, has a desired output power as compared with a third harmonic 3f0, a fourth harmonic 4f0, or a higher harmonic of the second harmonic 2f0 of the fundamental wave f0. And a plurality of frequency doublers corresponding to the target frequency, for example, three frequency doublers corresponding to a multiplication factor of 8 because the local oscillator is advantageous in terms of design. Is constructed by cascade-connecting four frequency doublers for a multiplier of 16.

Conventionally, for example, the prior art document "A 15/60 ON
E-STAGE MMIC FREQUENCY QUADRUPUTUR ”IEEE 1996 Mic
rowave and Millimeter-Wave Monolithic Circuits Sym
A frequency quadrupler is known from posium pages 35-38. As shown in FIG. 13, the conventional frequency quadrupler includes an input matching circuit 10, a high electron mobility transistor (hereinafter, referred to as HEMT) 11, which is a nonlinear element for frequency multiplication in a microwave band, and an input side. Transmission line 12
1. Output-side transmission line 122, open-end stub 124 of １ ／ wavelength of fundamental wave f0 for output-side transmission line, open-end stub 125 of １ ／ wavelength of second harmonic 2f0 for output-side transmission line, input-side transmission Open-ended stub 127 of 1/4 wavelength of 2f2f0 for the line, open-ended stub 12 of 1/4 wavelength of 4f0 for 4f0 for the input-side transmission line
8 and an output matching circuit 13.

In the above known frequency quadrupler, HE
Among the nonlinear conversion signals output from the MT 11 to the drain-side output transmission line 122, the fundamental wave component f 0 and the second harmonic wave component 2 f 0 have a tip of １ ／ wavelength with respect to the fundamental wave f 0 connected to the output transmission line 122. Open stub 124, 2
1/4 wavelength open end stub 125 for harmonic 2f0
While the second harmonic component 2f0 and the fourth harmonic component 4f0 transmitted from the HEMT 11 to the input side are
2 connected to the transmission line 121 on the base side of the EMT 11
Open end stub 127 of 1/4 wavelength with respect to harmonic 2f0
1/4 wavelength open-end stub 1 with respect to the fourth harmonic 4f0
28 and transmission to the input side is suppressed.
Thus, the fourth harmonic signal obtained by frequency-converting the fundamental wave f0 by the HEMT 11 is output to the output terminal 2.

[0009] However, the known frequency quadrupler basically comprises four quarter-wave open-end stubs 12.
4, 125, 127 and 128, and the output transmission line 122 of the HEMT 11 in this frequency quadrupler includes a so-called third harmonic trap circuit for suppressing the power of the third harmonic component. In addition, the entire frequency multiplier is large and the circuit configuration is complicated.

The conventional frequency band multiplier of the microwave band or millimeter wave band is basically constituted by cascading at least three or more frequency doublers.
The entire multiplier is large and consumes a lot of power,
There is a disadvantage that the conversion efficiency is still unsatisfactory.

[0011]

SUMMARY OF THE INVENTION A first object of the present invention is to improve a conventional frequency multiplier, particularly a microwave or millimeter-wave frequency multiplier, and to improve the frequency multiplier of the third harmonic. The output power can be effectively suppressed, and the suppressed power can be distributed to the fourth harmonic.
(Multiplier).

A second object of the present invention is to provide a frequency multiplier which is low in power consumption, small in size and inexpensive in manufacturing cost.

[0013]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a fundamental wave suppression circuit, a second harmonic wave suppression circuit and a third harmonic wave suppression circuit in an output transmission line of a microwave transistor for nonlinearly converting a microwave input signal. A harmonic suppression circuit is provided to output a signal obtained by multiplying the frequency f0 of the microwave input signal by four.

[0014]

FIG. 1 shows a frequency multiplier 25 including a frequency doubling circuit according to the present invention and a known frequency doubler 26.
An example of a two-stage frequency multiplier 24 formed by serially connecting the two is shown. The frequency multiplier 24 includes a frequency doubling circuit 25 in a first stage and a frequency doubling circuit 26 in a second stage. The first stage frequency doubling circuit is a signal source 23 using a phase locked oscillator (PLO) used in, for example, a mobile communication system.
Receives an input signal in the microwave band from, and generates a fourth harmonic signal obtained by multiplying the frequency f0 of the input signal by four times. The fourth harmonic signal is applied to a second-stage frequency doubling circuit 26. From the doubling circuit 26, an eighth harmonic signal 8f0 obtained by doubling the frequency 4f0 of the fourth harmonic signal by a known method is obtained. Output to the output terminal.

A two-stage frequency multiplier (8-times multiplier) having the above configuration
Thus, for example, when the frequency f0 of the microwave input signal is 1.9 GHz, the frequency octupler gives 1.9 GHz.
A signal of about 15 GHz multiplied by z × 8 is output.

FIG. 2 shows an embodiment of a 30 GHz band frequency synthesizer constructed using the frequency multiplier of the present invention. In FIG. 2, as in the case of FIG.
A super-high frequency signal f0 in the GHz band is generated, and the super-high frequency output is applied to the three-stage frequency multiplier 24 of the present invention. The three-stage frequency multiplier 24 is constructed by connecting a known frequency doubler in series with the two-stage frequency multiplier of FIG. 1, that is, the third stage of the frequency multiplier 24 has a frequency doubling circuit 2.
7 are connected in cascade. The three-stage frequency multiplier 24 multiplies the frequency f0 of the ultrahigh-frequency signal from the signal source 23 four times by the first-stage frequency quadrupling circuit 25, and then multiplies the fourth harmonic signal by the second frequency multiplier 25. The frequency doubling circuit 26 of the second stage doubles the frequency and converts it into an eighth harmonic, and furthermore, the eighth harmonic signal is doubled by the third frequency doubling circuit 27 to 16 times.
This is converted into a harmonic wave, and this 16th harmonic wave, that is, 30 GHz obtained by multiplying the frequency 1.9 GHz of the ultrahigh frequency input signal by 16 times
An output signal of the z band is output to the output terminal 2.

Next, a frequency multiplier (quadrupler) of the present invention applicable to the frequency synthesizer shown in FIGS.
Will be described with reference to FIG.

The frequency multiplier of the present invention basically has the configuration shown in FIG.
As shown in (1), a microwave input signal input to the input terminal 1 is input to a nonlinear microwave transistor 32 via an input matching circuit 31 designed in accordance with the frequency f0 of the input signal. Transistor 32
As a result, the microwave input signal is nonlinearly converted and transmitted to the output transmission line of the transistor 32. The distortion signal including the non-linearly converted multiplied wave, that is, the signal including the fundamental wave, the second harmonic wave, and the third harmonic component is supplied to the fundamental wave suppressing circuit or the f0 trap circuit 34, 2 connected to the output transmission line.
The output power of the fundamental, second and third harmonic components is suppressed by the harmonic suppression circuit or 2f0 trap circuit 33, the third harmonic suppression circuit or 3f0 trap circuit 35, and the output matching circuit 36 is matched to the fourth harmonic 4f0. The fourth harmonic signal is output to the output terminal 2 via the.

In the frequency multiplier (quadruple) configured as described above, the output power of the third harmonic component is suppressed by the third harmonic trap circuit 35, so that the power is efficiently distributed to the fourth harmonic component. The conversion gain can be more effectively increased.

As the microwave transistor 32, for example, a high electron mobility transistor (HEMT)
Or heterojunction bipolar transistor (HBT)
For example, a non-linear element operable at a high frequency can be used.

By cascade-connecting a plurality of n (n = 2, 3, 4,...) Frequency doublers to the output stage of the frequency multiplier (quadruple) having the above configuration, 8 × n times, that is, 16 times multiplier, 3
It can be a doubler or the like.

FIG. 5 shows a specific example in which the frequency multiplier of the present invention shown in FIG. 3 is constituted by using a field effect transistor (FET) as the microwave transistor 32.
In FIG. 5, the microwave input signal input to the input terminal 1 is input to the gate of the FET 32 through the input matching circuit 31 corresponding to the frequency f0 of the input signal.
32, the frequency f0 of the input signal
Is output. Of the multiplied wave outputs from the FET 32, the fundamental wave f0, the second harmonic wave 2f0 and the third harmonic wave 2f0 connected to the output transmission line on the drain side of the FET 32.
The output power thereof is suppressed by the suppression circuit or the trap circuits 34, 33 and 35 for the harmonic 3f0. With this configuration, a fourth harmonic signal whose power is intensively distributed is output from the output end of the output transmission line of the FET 32, and the fourth harmonic signal is an output matching circuit corresponding to the frequency 4f0 of the fourth harmonic signal. The signal is output to the output terminal 2 via.

The fundamental wave f in the frequency multiplier having the above configuration.
As shown in FIG. 5, the 0th, 2nd harmonic 2f0 and 3rd harmonic trap circuits are lumped constant circuits each composed of a capacitor C0 and a reactance L0, a capacitor C2 and a reactance L2, and a capacitor C3 and a reactance L3. You. Note that these trap circuits 34, 33,
Numeral 35 denotes 代 え of the fundamental wave f0, the second harmonic 2f0, and the third harmonic 3f0 as shown in FIG. 6 instead of the lumped constant circuit.
It can be configured using an open stub whose wavelength has an open end. In the frequency multiplier of FIG.
Only the f0 trap circuit or the suppression circuit 30 has the third harmonic 3
A configuration using an open stub with an open end at a quarter wavelength of f0 is shown.

The third harmonic trap circuit or suppression circuit 35
The frequency spectrum of the output power during the operation of the conventional frequency quadrupler having no frequency multiplier and the frequency quadrupler according to the present invention having the third harmonic trap circuit or the suppression circuit 35 as shown in FIG. , Respectively, FIG.
(A) and (b). As shown in the frequency spectra of FIGS. 8A and 8B, the third harmonic trap circuit 3
5, the output power of the third harmonic is approximately 28 dB.
While suppressing the output, the output of the fourth harmonic wave could be increased by about 2 dB.

FIG. 7 shows a configuration of a frequency doubler applicable to the frequency multiplier (8 ×, 16 ×, etc.) of the present invention. This frequency doubler is configured by using an FET 32 that can obtain a desired multiplication gain as a microwave transistor for nonlinearly converting a microwave input signal, as in the conventional type. An input matching circuit 31 corresponding to the frequency f0 of the input signal is connected to the input terminal of the FET 32, and an open stub 39 of a quarter wavelength of the fundamental wave f0 for suppressing the fundamental wave component on the output transmission line of the FET 32.
And an output matching circuit 38 corresponding to the second harmonic frequency 2f0 is connected to the output end of the output transmission line. The output of the frequency doubler is output to the output terminal 2 via the filter capacitor C.

As the band-pass filter 28 applicable to the local oscillator 40 shown in FIG. 4, for example, a type shown in FIG. 9 can be used. The band pass filter 28 shown in FIG. 9 is configured by four microstrip lines 37, 37, 38, 38. By changing the line length and width of these microstrip lines and the distance between the lines, a filter having desired filtering characteristics is formed.

As the input matching circuit 31 and the output matching circuit 36 in the frequency multiplier of the present invention, for example, FIG.
Can be used. The matching circuit shown in FIG. 10 includes four transmission lines 47 whose line lengths are adjustable, a bias voltage terminal 46 and a bias resistor 4.
5 and a bias circuit constituted by the bias circuit 5. The line length of each transmission line 47 is adjustable, and by changing these line lengths, it is possible to adjust to a desired impedance.

Next, FIG. 4 shows a local oscillator 40 constructed by using the frequency multiplier (8-fold multiplier) of the present invention shown in FIG.
1 shows an embodiment of a transmission / reception device including the above. In FIG. 4, FIG.
The signal including the fourth harmonic component output from the frequency multiplier 24 and the transmission signal output from the transmission signal generator 41 are mixed by the frequency mixer 42 to generate a microwave band or millimeter signal. The transmitting wave in the waveband is transmitted by the transmitting device 43.
, And transmission is performed in this manner. On the other hand, a signal wave received by an antenna of a receiving device (not shown) is mixed by a local oscillator (not shown) and a frequency mixer similar to those in the transmitting device, and a transmission signal is reproduced.

[0029]

The frequency multiplier according to the present invention is different from the conventional type in that the output transmission line of the microwave transistor for nonlinearly converting the microwave input signal includes only the fundamental wave suppressing circuit and the second harmonic wave suppressing circuit. Instead, a third harmonic suppression circuit is provided, so that the output power of the third harmonic is more effectively suppressed than that of the conventional type, and the suppressed power is distributed to the fourth harmonic. The conversion efficiency of the vessel can be effectively increased.

In the first stage, a frequency multiplier having the above configuration is provided.
(Quadrupler), and at least one or more frequency doublers are cascaded to the first stage frequency multiplier (quadrupler) to form an even multiple of 8 or more. Therefore, the number of nonlinear elements for one stage can be reduced as compared with the conventional type, so that the power consumption of the multiplier can be reduced, the size of the entire multiplier can be reduced, and the manufacturing cost can be effectively reduced. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of a frequency multiplier (8-fold multiplier) according to the present invention.

FIG. 2 is a block circuit diagram of a frequency multiplier (16-fold multiplier) of the present invention.

FIG. 3 is a block circuit diagram of a frequency multiplier (quadrupler) of the present invention.

FIG. 4 is a block circuit diagram of the transmission / reception device of the present invention.

FIG. 5 is a circuit diagram of an embodiment of a frequency quadrupler according to the present invention.

FIG. 6 is a circuit diagram of a modified example of the frequency quadrupler according to the present invention.

7 is a subsequent stage (second stage) in the frequency multiplier of FIG. 1;
3 is a circuit diagram of a frequency doubling circuit of FIG.

8 is a spectrum diagram showing a frequency-output power characteristic of the frequency multiplier (quadrupler) shown in FIG. 5; FIG. 8A is a spectrum showing an output characteristic of a frequency quadrupler having a third harmonic trap circuit; It is a figure, (b) is a spectrum figure showing the output characteristic of the frequency quadrupler which does not include a 3rd harmonic trap circuit.

FIG. 9 is a schematic configuration diagram of an embodiment of a bandpass filter applicable to the present invention.

FIG. 10 is a block circuit diagram of a matching circuit applicable to the present invention.

FIG. 11 is a block circuit diagram of a conventional frequency multiplier.

FIG. 12 is a block circuit diagram of a conventional frequency multiplier (8-fold multiplier).

FIG. 13 is a circuit diagram showing a basic configuration of a conventionally known frequency multiplier (quadrupler).

[Explanation of symbols]

 Reference Signs List 1 input terminal 2 output terminal 3 microwave signal source 4 frequency doubler 5 frequency doubler 6 frequency doubler 7 frequency doubler 8 bandpass filter 10 input (f0) matching circuit 11 microwave transistor (nonlinear element) 12 Band stop circuit 121 Microwave signal transmission line 124 Tip open stub for fundamental wave 125 Tip open stub for 2nd harmonic 127 Tip open stub for 2nd harmonic 128 128 Tip open stub for 4th harmonic 13 Output (nf0) matching circuit 23 Microwave Band-Phase Locked Oscillator (PLO) 24 Frequency Multiplier 25 Frequency Quadruple Circuit (First Stage) 26 Frequency Doubler (Second Stage) 27 Frequency Doubler (Third Stage) 30 Open Stub 31 f0 (Basic Wave) ) Matching circuit 32 Microwave transistor (FET) 33 2f0 (2nd harmonic) trap circuit (suppression circuit) 34 f 0 (fundamental wave) trap circuit (suppression circuit) 35 3f0 (3rd harmonic) trap circuit (suppression circuit) 36 output (4f0) matching circuit 37 microstrip line 38 microstrip line 39 open stub 40 local oscillator 41 transmission signal generator 42 mixer 43 transmitting device (antenna) 45 resistor 46 bias voltage terminal 47 transmission line 48 trap circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J067 AA01 AA04 CA36 CA92 FA20 HA09 HA29 HA33 KA00 KA12 KA29 KA32 KA41 KA44 KA68 KS11 KS28 LS12 SA13 TA01 TA03 5K011 DA03 DA05 DA27 EA01 JA01 KA03

Claims (8)

[Claims] An output transmission line of a microwave transistor for non-linearly converting a microwave input signal is provided with a fundamental wave suppressing circuit, a second harmonic wave suppressing circuit and a third harmonic wave suppressing circuit to reduce the frequency f0 of the microwave input signal. A frequency multiplier configured to output a signal multiplied by four. 2. The frequency multiplier according to claim 1, wherein the third harmonic suppression circuit is formed using a lumped constant circuit. 3. The frequency multiplier according to claim 1, wherein the third harmonic suppression circuit is configured using an open stub. 4. An input matching circuit corresponding to the frequency f0 of the microwave input signal is connected to the input terminal, and an output matching circuit corresponding to the fourth harmonic signal 4f0 is connected to the output terminal. The frequency multiplier according to any one of claims 1 to 3. 5. A frequency multiplier according to any one of claims 1 to 4, provided in a first stage, and a frequency doubler constituted by using a high-frequency transistor in the first stage frequency multiplier. The frequency f0 of the microwave input signal is multiplied by an even multiple of 8 or more by connecting at least one device in series, and a signal is output.
Multi-stage frequency multiplier. 6. A frequency multiplier according to claim 1, provided in a first stage, and one frequency doubler connected in series to said first stage frequency multiplier. A two-stage frequency multiplier formed with an eight-times frequency circuit. 7. A frequency multiplier according to any one of claims 1 to 4 provided in a first stage, and two frequency doublers are connected in cascade to said first stage frequency multiplier. A three-stage frequency multiplier formed with a 16-times frequency circuit. 8. A transmission / reception device comprising a frequency multiplier according to any one of claims 1 to 7 as a local oscillator of the transmission / reception device.