CN117579000A - W-band low-power-consumption six-frequency multiplier based on high conversion gain frequency doubler - Google Patents

Abstract

The invention discloses a W-band low-power-consumption hexamultiplier based on a high conversion gain frequency doubler, which comprises an input matching network, a tripler based on a Casode structure, an interstage matching network, a frequency doubler based on a Gilbert cell structure and an output matching network which are sequentially connected. The frequency multiplier is based on a Cascade structure, and the third harmonic output by the frequency multiplier is designed to drive the frequency doubler exactly, so that the frequency doubler obtains nearly saturated output power. The reduction in the output power requirements of the tripler also reduces efforts to suppress harmonics, saving power consumption. The frequency doubler is based on a Gilbert cell structure for realizing high conversion gain under low power consumption, and outputs a single end after the differential second harmonic is overlapped, so that the output power is further enhanced, and the conversion gain is improved.

Description

W-band low-power-consumption six-frequency multiplier based on high conversion gain frequency doubler

Technical Field

The invention belongs to the technical field of radio frequency integrated circuits, and particularly relates to a W-band low-power-consumption six-frequency multiplier based on a high conversion gain frequency doubler.

Background

The millimeter wave has a wavelength of between 1mm and 10mm and a corresponding frequency range of between 30GHz and 300 GHz. The millimeter wave has the wavelength between the overlapping wavelength of the microwave and the far infrared wave, so that the millimeter wave has the characteristics of the two spectrums, such as strong anti-interference capability, strong penetrating capability, extremely wide bandwidth, narrower wave beam, and the like, and can work all the day. In recent years, millimeter wave technology has been widely used in the fields of radar and guidance systems, electronic countermeasure, broadband communication, radio astronomy, millimeter wave imaging, and the like. The frequency multiplier provides local oscillation signal source for the frequency mixer, and is an important component module in millimeter wave signal link. At low frequencies, the signal source is typically directly generated by the voltage controlled oscillator, but due to parasitic effects and passive device losses, the phase noise and stability of the signal generated by the voltage controlled oscillator are continually degraded by the increase in frequency. It is therefore not feasible to directly generate the signal source with a voltage controlled oscillator in the millimeter wave band. The nonlinear operation of the device is used to expand the low-frequency signal generated by the voltage-controlled oscillator to a very high-frequency signal, but the additional circuit increases the area and power consumption of the chip. Therefore, the design of the frequency multiplier with low power consumption, high efficiency and compact structure has important significance.

The frequency doubler is mainly divided into a passive frequency doubler and an active frequency doubler. Active frequency multipliers typically use the nonlinear impedance characteristics of transistors to generate the desired harmonics, most notably with the need for a dc power supply. The dc bias of the transistor directly affects the frequency doubling efficiency. The frequency multiplier has low frequency multiplication times, good isolation of input and output ports, low frequency conversion loss and broadband characteristics. The active frequency doubler requires lower driving power than the passive frequency doubler, while also having some signal gain. The frequency multiplication efficiency of a single-tube frequency multiplier is attenuated as the square of the frequency multiplication times, so that higher order frequency multipliers are usually realized by cascading or stacking lower order frequency multipliers for better performance. In the design process of the high-order frequency multiplier, a power amplifier and a filter are often used to realize higher output power and harmonic suppression, but the circuit structure is easy to be complicated, and the power consumption is too high. When the nonlinear frequency multiplication is realized by using the device, only a small part of direct current power in the frequency multiplier is converted into harmonic power, and most of the direct current power is converted into fundamental wave power, so that the direct current conversion efficiency is lower. In contrast, the frequency doubler based on the Gilbert cell structure can realize the function of doubling the signal frequency by utilizing the circuit structure, and can generate a signal with high conversion gain more easily under lower power consumption.

Therefore, providing a frequency multiplier with low power consumption and high power has become a problem to be solved.

Disclosure of Invention

In order to solve the problems in the prior art, the invention provides a W-band low-power-consumption six-frequency multiplier based on a high conversion gain frequency doubler. The technical problems to be solved by the invention are realized by the following technical scheme:

the utility model provides a W wave band low-power consumption six frequency doubler based on high conversion gain frequency doubler, W wave band low-power consumption six frequency doubler is including the input matching network, the tripler based on the Cascade structure, interstage matching network, the frequency doubler based on Gilbert cell structure and the output matching network that connect gradually, wherein:

the input matching network is used for receiving a radio frequency signal through an input end IN and converting the radio frequency signal into a first differential signal and a second differential signal;

the tripler is used for receiving the first differential signal and the second differential signal and generating two third harmonics after frequency tripling;

the interstage matching network is used for receiving the two third harmonics and resonating at the third harmonics so as to enable the two third harmonics to pass through and inhibit other harmonics;

the frequency doubler is used for enabling the two third harmonic waves to generate two sixth harmonic waves after frequency doubling;

the output matching network is used for enabling the two sixth harmonics to be overlapped and converted into a single-ended signal and outputting the single-ended signal through the signal output end OUT.

Optionally, the input matching network includes an input balun BL1, a capacitor C2, a capacitor C3, and a capacitor C4, where:

the input end of input balun BL1 is connected with input end IN, the first end of electric capacity C1 is connected the first output of input balun BL1 with the first end of electric capacity C3, the second end of electric capacity C1 is grounded, the second end of electric capacity C3 is connected the first input of tripler, the first end of electric capacity C2 is connected the second output of input balun BL1 and the first end of electric capacity C4, the second end of electric capacity C2 is grounded, the second end of electric capacity C4 is connected the second input of tripler.

Optionally, the capacitor C1, the capacitor C2, the capacitor C3, and the capacitor C4 each include a MIM capacitor.

Optionally, the tripler includes a transistor Q1, a transistor Q2, a transistor Q3, a transistor Q4, a resistor R1, a resistor R2, a capacitor C5, a capacitor C6, a transmission line TL1, and a transmission line TL2, wherein:

the base electrode of the transistor Q1 is connected with the first input end of the tripler and the first end of the resistor R1, the second end of the resistor R1 is connected with the bias voltage end Vb1, the emitter electrode of the transistor Q1 is grounded, and the collector electrode of the transistor Q1 is connected with the emitter electrode of the transistor Q2;

the base electrode of the transistor Q3 is connected with the second input end of the tripler and the first end of the resistor R2, the second end of the resistor R2 is connected with the bias voltage end Vb1, the emitter electrode of the transistor Q3 is grounded, and the collector electrode of the transistor Q3 is connected with the emitter electrode of the transistor Q4;

the base electrode of the transistor Q2 is connected to the first end of the transmission line TL1 and the first end of the resistor R3, the second end of the transmission line TL1 is connected to the first end of the capacitor C5, the second end of the capacitor C5 is grounded, the second end of the resistor R3 is connected to the bias voltage terminal Vb2, and the collector electrode of the transistor Q2 is connected to the first input end of the inter-stage matching network;

the base of the transistor Q4 is connected to the first end of the transmission line TL2 and the first end of the resistor R4, the second end of the transmission line TL2 is connected to the first end of the capacitor C6, the second end of the capacitor C6 is grounded, the second end of the resistor R4 is connected to the bias voltage terminal Vb2, and the collector of the transistor Q4 is connected to the second input end of the inter-stage matching network.

Optionally, the inter-stage matching network includes a transformer TF1, an inductor L2, an inductor L3, and an inductor L4, where:

a first end of the inductor L1 is connected with a first input end of the interstage matching network, and a second end of the inductor L1 is connected with a first input end of the transformer TF 1;

a first end of the inductor L2 is connected with a second input end of the interstage matching network, and a second end of the inductor L2 is connected with a second input end of the transformer TF 1;

a first end of the inductor L3 is connected with a first output end of the transformer TF1 and a first input end of the frequency doubler, and a second end of the inductor L3 is grounded;

the first end of the inductor L4 is connected with the second output end of the transformer TF1 and the second input end of the frequency doubler, and the second end of the inductor L4 is grounded.

Optionally, the frequency doubler includes a transistor Q5, a transistor Q6, a transistor Q7, a transistor Q8, a transistor Q9, a transistor Q10, a capacitor C7, a capacitor C8, a capacitor C9, a capacitor C10, a resistor R5, a resistor R6, a resistor R7, and a resistor R8, wherein:

the first end of the capacitor C7 and the first end of the capacitor C9 are both connected with the first input end of the frequency doubler, the second end of the capacitor C7 is connected with the first end of the resistor R5, the base electrode of the transistor Q7 and the base electrode of the transistor Q10, the second end of the resistor R5 is connected with the bias voltage end Vb3, the second end of the capacitor C9 is connected with the first end of the resistor R7 and the base electrode of the transistor Q5, and the second end of the resistor R7 is connected with the bias voltage end Vb4;

the collector of the transistor Q7 is connected with the collector of the transistor Q9 and the first input end of the output matching network, the emitter of the transistor Q7 is connected with the emitter of the transistor Q8 and the collector of the transistor Q5, the emitter of the transistor Q5 is grounded, the collector of the transistor Q10 is connected with the collector of the transistor Q8 and the second input end of the output matching network, the emitter of the transistor Q10 is connected with the emitter of the transistor Q9 and the collector of the transistor Q6, and the emitter of the transistor Q6 is grounded;

the first end of the capacitor C8 and the first end of the capacitor C10 are both connected with the second input end of the frequency doubler, the second end of the capacitor C8 is connected with the first end of the resistor R6, the base electrode of the transistor Q8 and the base electrode of the transistor Q9, the second end of the capacitor C10 is connected with the first end of the resistor R8 and the base electrode of the transistor Q6, and the second end of the resistor R8 is connected with the bias voltage end Vb4.

Optionally, the capacitor C7, the capacitor C8, the capacitor C9, and the capacitor C10 each include a MIM capacitor.

Optionally, the output matching network includes an output balun BL2, a capacitor C11 and an inductance L5, where:

the first input end of the output balun BL2 is connected with the first input end of the output matching network, the second input end of the output balun BL2 is connected with the second input end of the output matching network, the first output end of the output balun BL2 is connected with the first end of the capacitor C11, the second output end of the output balun BL2 is grounded, the second end of the capacitor C11 is connected with the first end of the inductor L5 and the signal output end OUT, and the second end of the inductor L5 is grounded.

Optionally, the capacitor C11 includes a MIM capacitor.

Compared with the prior art, the invention has the beneficial effects that:

the W-band low-power-consumption six-frequency multiplier provided by the invention adopts a mode of cascading a frequency tripler and a frequency doubler, does not use an additional filter and a power amplifier, and has a simple structure. The tripler is based on a Cascade structure, and the third harmonic output by the tripler is designed to drive the doubler exactly, so that the doubler obtains nearly saturated output power. The reduction in the output power requirements of the tripler also reduces efforts to suppress harmonics, saving power consumption. The frequency doubler is based on a Gilbert cell structure for realizing high conversion gain under low power consumption, and outputs a single end after the differential second harmonic is overlapped, so that the output power is further enhanced, and the conversion gain is improved.

The present invention will be described in further detail with reference to the accompanying drawings.

Drawings

FIG. 1 is a schematic diagram of a W-band low-power-consumption six-frequency multiplier based on a high conversion gain frequency doubler according to an embodiment of the present invention;

FIG. 2 is a circuit diagram of a W-band low-power-consumption six-frequency multiplier based on a high conversion gain frequency doubler according to an embodiment of the present invention;

FIG. 3 is a graph of simulation results of the output power of a frequency tripler as a function of input power provided by an embodiment of the present invention;

FIG. 4 is a graph of simulation results of output power of a frequency doubler according to an embodiment of the present invention as a function of input power;

FIG. 5 is a graph of simulation results of output power of a hexamultiplier according to input power according to an embodiment of the present invention;

fig. 6 is a graph of simulation results of power added efficiency of a hexamultiplier according to input power according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to specific examples, but embodiments of the present invention are not limited thereto.

Example 1

Referring to fig. 1, fig. 1 is a schematic diagram of a W-band low-power-consumption six-frequency multiplier based on a high conversion gain frequency doubler according to an embodiment of the present invention. The invention provides a W-band low-power-consumption frequency hexamultiplier based on a high conversion gain frequency doubler, which comprises an input matching network, a tripler based on a Casode structure, an interstage matching network, a frequency doubler based on a Gilbert cell structure and an output matching network which are sequentially connected, wherein:

the input matching network is used for receiving the radio frequency signal through the input end IN and converting the radio frequency signal into a first differential signal and a second differential signal;

the frequency tripler is used for receiving the first differential signal and the second differential signal and generating two third harmonics after frequency tripling;

the interstage matching network is used for receiving the two third harmonics and resonating at the third harmonics so as to enable the two third harmonics to pass through and inhibit other harmonics;

the frequency doubler is used for doubling the frequency of the two third harmonics to generate two sixth harmonics;

and the output matching network is used for enabling the two sixth harmonics to be overlapped and converted into a single-ended signal and outputting the single-ended signal through the signal output end OUT.

Specifically, the hexamultiplier is formed by cascading a tripler based on a Cascade structure and a double multiplier based on a Gilbert cell structure through a matching network. The radio frequency signal is input from the input end IN, and the signal is output from the output end OUT after six times of frequency multiplication. The radio frequency signal is converted into a differential signal through an on-chip balun and is input into a frequency tripler to generate third harmonic, the interstage matching network inputs purer third harmonic into a frequency doubler, the third harmonic generates sixth harmonic after frequency doubling, and finally double-end sixth harmonic is overlapped and converted into a single-ended signal through the on-chip balun. The frequency doubler based on the Gilbert cell structure can realize higher conversion gain under low power consumption, and the output power of the frequency doubler based on the Cascade structure can just drive the frequency doubler, so that the frequency doubler realizes nearly saturated output power. Because of the higher conversion gain of the frequency doubler, the frequency doubler only needs to provide the third harmonic of lower power, and the power consumption of the whole circuit is further reduced.

In an alternative embodiment, referring to fig. 2, the input matching network includes an input balun BL1, a capacitor C2, a capacitor C3, and a capacitor C4, wherein:

the input end of the input balun BL1 is connected with the input end IN, the radio frequency signal is provided from the outside of the chip and is input to the input balun BL1 through the input end IN, the first end of the capacitor C1 is connected with the first output end of the input balun BL1 and the first end of the capacitor C3, the second end of the capacitor C1 is grounded, the second end of the capacitor C3 is connected with the first input end of the tripler, the first end of the capacitor C2 is connected with the second output end of the input balun BL1 and the first end of the capacitor C4, the second end of the capacitor C2 is grounded, and the second end of the capacitor C4 is connected with the second input end of the tripler.

Preferably, the capacitor C1, the capacitor C2, the capacitor C3 and the capacitor C4 each comprise MIM capacitors.

In an alternative embodiment, please continue to refer to fig. 2, the tripler includes a transistor Q1, a transistor Q2, a transistor Q3, a transistor Q4, a resistor R1, a resistor R2, a capacitor C5, a capacitor C6, a transmission line TL1, and a transmission line TL2, wherein:

the base of the transistor Q1 is connected with the first input end of the tripler and the first end of the resistor R1, namely, the base of the transistor Q1 is connected with the second end of the capacitor C3 and the first end of the resistor R1, the second end of the resistor R1 is connected with the bias voltage end Vb1, the emitter of the transistor Q1 is grounded, and the collector of the transistor Q1 is connected with the emitter of the transistor Q2;

the base of the transistor Q3 is connected with the second input end of the tripler and the first end of the resistor R2, namely, the base of the transistor Q3 is connected with the second end of the capacitor C4 and the first end of the resistor R2, the second end of the resistor R2 is connected with the bias voltage end Vb1, the emitter of the transistor Q3 is grounded, and the collector of the transistor Q3 is connected with the emitter of the transistor Q4;

the base electrode of the transistor Q2 is connected with the first end of the transmission line TL1 and the first end of the resistor R3, the second end of the transmission line TL1 is connected with the first end of the capacitor C5, the second end of the capacitor C5 is grounded, the second end of the resistor R3 is connected with the bias voltage end Vb2, and the collector electrode of the transistor Q2 is connected with the first input end of the inter-stage matching network;

the base of the transistor Q4 is connected to the first end of the transmission line TL2 and the first end of the resistor R4, the second end of the transmission line TL2 is connected to the first end of the capacitor C6, the second end of the capacitor C6 is grounded, the second end of the resistor R4 is connected to the bias voltage end Vb2, and the collector of the transistor Q4 is connected to the second input end of the inter-stage matching network.

Specifically, the tripler adopts a Cascode structure, the transistor Q1 and the transistor Q3 are connected by common emitters, are biased in a nonlinear region to obtain rich harmonics, and the base bias voltage is adjusted to maximize the third harmonic component. The transistor Q2 and the transistor Q4 are connected by a common base electrode, so that the conversion loss of the transistor Q1 and the transistor Q3 is compensated, and the isolation degree is improved. The collector voltage of the transistor Q2 is reduced by the transmission line TL1 and the capacitor C5, the collector voltage of the transistor Q4 is reduced by the transmission line TL2 and the capacitor C6, the load voltage difference is increased, a larger current is obtained, and the output power of the third harmonic is improved.

Further, the power supply voltage (VDD 1) was 2.5V, the common emitter bias voltage (Vb 1) was 850mV, and the common base bias voltage (Vb 2) was 1.6V.

Here, the reference layers of the transmission lines TL1 and TL2 are each selected as a LY layer metal (aluminum).

In an alternative embodiment, please continue to refer to fig. 2, the inter-stage matching network includes a transformer TF1, an inductance L2, an inductance L3, and an inductance L4, wherein:

a first end of the inductor L1 is connected with a first input end of the inter-stage matching network, namely, a first end of the inductor L1 is connected with a collector electrode of the transistor Q2, and a second end of the inductor L1 is connected with a first input end of the transformer TF 1;

a first end of the inductor L2 is connected with a second input end of the interstage matching network, a first end of the inductor L2 is connected with a collector electrode of the transistor Q4, and a second end of the inductor L2 is connected with a second input end of the transformer TF 1;

the first end of the inductor L3 is connected with the first output end of the transformer TF1 and the first input end of the frequency doubler, and the second end of the inductor L3 is grounded;

the first end of the inductor L4 is connected with the second output end of the transformer TF1 and the second input end of the frequency doubler, and the second end of the inductor L4 is grounded.

In an alternative embodiment, please continue to refer to fig. 2, the frequency doubler includes a transistor Q5, a transistor Q6, a transistor Q7, a transistor Q8, a transistor Q9, a transistor Q10, a capacitor C7, a capacitor C8, a capacitor C9, a capacitor C10, a resistor R5, a resistor R6, a resistor R7, and a resistor R8, wherein:

the first end of the capacitor C7 and the first end of the capacitor C9 are both connected with the first input end of the frequency doubler, namely the first end of the capacitor C7 and the first end of the capacitor C9 are both connected with the first end of the inductor L3, the second end of the capacitor C7 is connected with the first end of the resistor R5, the base of the transistor Q7 and the base of the transistor Q10, the second end of the resistor R5 is connected with the bias voltage terminal Vb3, the second end of the capacitor C9 is connected with the first end of the resistor R7 and the base of the transistor Q5, and the second end of the resistor R7 is connected with the bias voltage terminal Vb4;

the collector of the transistor Q7 is connected with the collector of the transistor Q9 and the first input end of the output matching network, the emitter of the transistor Q7 is connected with the emitter of the transistor Q8 and the collector of the transistor Q5, the emitter of the transistor Q5 is grounded, the collector of the transistor Q10 is connected with the collector of the transistor Q8 and the second input end of the output matching network, the emitter of the transistor Q10 is connected with the emitter of the transistor Q9 and the collector of the transistor Q6, and the emitter of the transistor Q6 is grounded;

the first end of the capacitor C8 and the first end of the capacitor C10 are both connected with the second input end of the frequency doubler, namely the first end of the capacitor C8 and the first end of the capacitor C10 are both connected with the first end of the inductor L4, the second end of the capacitor C8 is connected with the first end of the resistor R6, the base of the transistor Q8 and the base of the transistor Q9, the second end of the capacitor C10 is connected with the first end of the resistor R8 and the base of the transistor Q6, and the second end of the resistor R8 is connected with the bias voltage end Vb4.

Specifically, the frequency doubler adopts a Gilbert cell structure. The common base connected transistors Q7 and Q10, and Q8 and Q9 alternately transmit signals generated at the collectors of the common emitter connected transistors Q5 and Q6 to out1 and out2. And finally, the on-chip balun is used for converting the differential signal into a single-ended signal and outputting the single-ended signal from an OUT end, so that the output power and conversion gain of the second harmonic are further improved.

Further, the power supply voltage (VDD 2) was 2.5V, the common emitter bias (Vb 4) was 860mV, and the common base bias (Vb 3) was 1.4V.

Preferably, the capacitor C7, the capacitor C8, the capacitor C9 and the capacitor C10 each comprise MIM capacitors.

In an alternative embodiment, please continue to refer to fig. 2, the output matching network includes an output balun BL2, a capacitor C11, and an inductance L5, wherein:

the first input end of the output balun BL2 is connected with the first input end of the output matching network, namely the first input end of the output balun BL2 is connected with the collector of the transistor Q7 and the collector of the transistor Q9, the second input end of the output balun BL2 is connected with the second input end of the output matching network, namely the second input end of the output balun BL2 is connected with the collector of the transistor Q8 and the collector of the transistor Q10, the first output end of the output balun BL2 is connected with the first end of the capacitor C11, the second output end of the output balun BL2 is grounded, the second end of the capacitor C11 is connected with the first end of the inductor L5 and the signal output end OUT, and the second end of the inductor L5 is grounded.

The present embodiment uses SiGe BiCMOS technology, and all the transistors used for the rf path are HBJTs with high characteristic frequencies.

The six-fold frequency device of this embodiment has an application frequency of 84GHz, belonging to the W-band.

The six-frequency multiplier provided by the embodiment is formed by connecting a frequency tripler and a frequency doubler through an input matching network, an interstage matching network and an output matching network which are formed by balun, a transformer, an inductor and a capacitor. The maximum output power is 1dBm, the harmonic suppression is about 20dBc, the maximum power additional efficiency is about 2.65%, and the direct current power consumption is only 35.5mW.

The integral six-frequency device structure diagram of the invention is shown IN figure 1, the radio frequency signal input end is IN, and the radio frequency signal output end is OUT; VDD1 and VDD2 are respectively power supply voltages for supplying six frequency multipliers outside the chip, and the voltage is 2.5V; vb1 and Vb2 are respectively common emitter bias and common base bias which are supplied to the tripler from the chip, and the voltage is respectively 850mV and 1.6V; vb4 and Vb3 are common emitter bias and common base bias supplied to the doubler off-chip, respectively, and the voltages are 860mV and 1.4V, respectively.

Table 1 shows parameter values of each device of the six frequency doubler provided by the invention, wherein the parameter values of the transistors are expressed as emitter length x emitter width x parallel number; the transmission line models all use E1 as a signal layer, LY as a reference layer, and the parameters are expressed as the length multiplied by the width of the signal line.

TABLE 1 element parameter values for the six-fold frequency device

Element name	Parameter value
		Transistors Q1/Q3	0.12μm×10μm×1
Transistors Q2/Q4	0.12μm×5μm×1
		Transistors Q5/Q6	0.12μm×7.5μm×1
Transistors Q7 to Q10	0.12μm×3.5μm×1
		Resistor R1/R2	90Ω
Resistor R3/R4	45Ω
		Resistors R5 to R7	3.6kΩ
Capacitance C1/C2	200fF
		Capacitance C3/C4	400fF
Capacitance C5/C6	50fF
		Capacitors C7-C10	100fF
Capacitor C11	90fF
		Inductance L1/L2	310pH
Inductance L3/L4	63.8pH
		Inductance L5	229pH
Transmission line TL1/TL2	178μm×4μm

The invention designs the ultra-low power consumption W-band six-frequency multiplier by adopting a mode of cascading the tripler and the frequency doubler, and has simple structure without using an additional filter and a power amplifier. The frequency doubler is based on a Gilbert cell structure which realizes high conversion gain under low power consumption, and the output balun is used for outputting single end after superposing differential second harmonic, so that the output power is further enhanced, and the conversion gain is improved. The tripler is based on a Cascade structure, and the third harmonic output by the tripler is designed to drive the doubler exactly, so that the doubler obtains nearly saturated output power. The reduction in the output power requirements of the tripler also reduces efforts to suppress harmonics, saving power consumption.

The simulation results of this circuit will now be described in detail for a more complete description of the hexamultiplier of the present invention.

All simulation results for the six-fold frequency device of the invention are post-simulation results. At this time, parasitic parameters of the bipolar transistor are extracted by using a PEX tool in Cadence, the rest of the parasitic transistors are subjected to electromagnetic simulation by using an electromagnetic simulation tool Momentum in ADS, and the result obtained by the combined simulation is closer to the real result of chip test.

The simulation result of the output power of the tripler as a function of input power is shown in fig. 3. The input power is larger than-2 dBm, the output power is larger than-4 dBm, and the inhibition of fundamental waves and second harmonic waves is larger than 10dBc. The requirement of driving the frequency doubler is met (simulation results of the frequency doubler show that when the input power is about-5 dBm, the output power is close to saturation, and when the harmonic power of the input signal is lower than 6dB of the fundamental wave, the output second harmonic suppresses other harmonics by more than 20 dBc).

The simulation result of the output power variation with the input power of the frequency doubler at 42GHz is shown in fig. 4. Due to incomplete symmetry of the layout, the doubler produces odd harmonics, but the rejection is greater than 30dBc. With the reduction of the input power, the output power of the frequency doubler still remains relatively stable, and higher conversion gain is shown.

The simulation result of the output power of the hexamultiplier as a function of the input power is shown in fig. 5. The sixth harmonic reaches the maximum output power of 1dBm when the input power is-1.5 dBm, the conversion gain is 2.5dBm, and the corresponding harmonic suppression is greater than 20dBc@84GHz. The simulation result of the power added efficiency with the input power change at the input signal frequency of 14GHz is shown in FIG. 6. When the input power is-1.5 dBm, the additional efficiency of the power reaches 2.65 percent. Exhibiting higher power added efficiency.

In summary, the input of the 14GHz signal of-1.5 dBm has the sixth harmonic output power of 1dBm, the harmonic suppression of about 20dBc and the power added efficiency of about 2.65%. The power supply is powered by adopting 2.5V power supply voltage, and the direct current power consumption is only 35.5mW. The six-frequency multiplier can work under extremely low power consumption and shows better performance.

The invention realizes a six-frequency multiplier working at 84GHz, and has excellent performance in millimeter wave frequency bands. The input of the 14GHz signal with the frequency of-1.5 dBm is realized, the output power of the sixth harmonic of the six-frequency device is 1dBm, the harmonic suppression is about 20dBc, the power addition efficiency is about 2.65%, and the direct current power consumption is only 35.5mW.

The invention designs a six-frequency multiplier by utilizing the high conversion gain characteristic of the frequency multiplier based on the Gilbert cell structure. The architecture improves the utilization rate of signal power among modules, realizes lower power consumption and obtains higher power additional efficiency;

the six-frequency multiplier of the invention does not additionally use a filter and a power amplifier, and the whole circuit structure is simpler.

It should be noted that the terms "first," "second," and "second" are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implying a number of technical features being indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more features. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Further, one skilled in the art can engage and combine the different embodiments or examples described in this specification.

Although the invention is described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings and the disclosure. In the description, the word "comprising" does not exclude other elements or steps, and the "a" or "an" does not exclude a plurality. Some measures are described in mutually different embodiments, but this does not mean that these measures cannot be combined to produce a good effect.

The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.

Claims (9)

1. The utility model provides a W wave band low-power consumption frequency hexamultiplier based on high conversion gain frequency doubler, its characterized in that, W wave band low-power consumption frequency hexamultiplier includes input matching network, the tripler based on the Casode structure, interstage matching network, the frequency doubler based on Gilbert cell structure and output matching network that connect gradually, wherein:

the input matching network is used for receiving a radio frequency signal through an input end IN and converting the radio frequency signal into a first differential signal and a second differential signal;

the tripler is used for receiving the first differential signal and the second differential signal and generating two third harmonics after frequency tripling;

the interstage matching network is used for receiving the two third harmonics and resonating at the third harmonics so as to enable the two third harmonics to pass through and inhibit other harmonics;

the frequency doubler is used for enabling the two third harmonic waves to generate two sixth harmonic waves after frequency doubling;

the output matching network is used for enabling the two sixth harmonics to be overlapped and converted into a single-ended signal and outputting the single-ended signal through the signal output end OUT.

2. The W-band low power hexamultiplier for high conversion gain multipliers of claim 1, wherein the input matching network comprises an input balun BL1, a capacitor C2, a capacitor C3 and a capacitor C4, wherein:

the input end of input balun BL1 is connected with input end IN, the first end of electric capacity C1 is connected the first output of input balun BL1 with the first end of electric capacity C3, the second end of electric capacity C1 is grounded, the second end of electric capacity C3 is connected the first input of tripler, the first end of electric capacity C2 is connected the second output of input balun BL1 and the first end of electric capacity C4, the second end of electric capacity C2 is grounded, the second end of electric capacity C4 is connected the second input of tripler.

3. The W-band low power hexamultiplier for high conversion gain multipliers according to claim 2, wherein the capacitor C1, the capacitor C2, the capacitor C3 and the capacitor C4 each comprise MIM capacitors.

4. The W-band low power hexamultiplier for high conversion gain multipliers of claim 1, wherein the tripler comprises transistor Q1, transistor Q2, transistor Q3, transistor Q4, resistor R1, resistor R2, capacitor C5, capacitor C6, transmission line TL1 and transmission line TL2, wherein:

the base electrode of the transistor Q1 is connected with the first input end of the tripler and the first end of the resistor R1, the second end of the resistor R1 is connected with the bias voltage end Vb1, the emitter electrode of the transistor Q1 is grounded, and the collector electrode of the transistor Q1 is connected with the emitter electrode of the transistor Q2;

the base electrode of the transistor Q3 is connected with the second input end of the tripler and the first end of the resistor R2, the second end of the resistor R2 is connected with the bias voltage end Vb1, the emitter electrode of the transistor Q3 is grounded, and the collector electrode of the transistor Q3 is connected with the emitter electrode of the transistor Q4;

the base electrode of the transistor Q2 is connected to the first end of the transmission line TL1 and the first end of the resistor R3, the second end of the transmission line TL1 is connected to the first end of the capacitor C5, the second end of the capacitor C5 is grounded, the second end of the resistor R3 is connected to the bias voltage terminal Vb2, and the collector electrode of the transistor Q2 is connected to the first input end of the inter-stage matching network;

the base of the transistor Q4 is connected to the first end of the transmission line TL2 and the first end of the resistor R4, the second end of the transmission line TL2 is connected to the first end of the capacitor C6, the second end of the capacitor C6 is grounded, the second end of the resistor R4 is connected to the bias voltage terminal Vb2, and the collector of the transistor Q4 is connected to the second input end of the inter-stage matching network.

5. The W-band low power hexamultiplier for high conversion gain multipliers of claim 1, wherein the inter-stage matching network comprises transformer TF1, inductor L2, inductor L3 and inductor L4, wherein:

a first end of the inductor L1 is connected with a first input end of the interstage matching network, and a second end of the inductor L1 is connected with a first input end of the transformer TF 1;

a first end of the inductor L2 is connected with a second input end of the interstage matching network, and a second end of the inductor L2 is connected with a second input end of the transformer TF 1;

a first end of the inductor L3 is connected with a first output end of the transformer TF1 and a first input end of the frequency doubler, and a second end of the inductor L3 is grounded;

the first end of the inductor L4 is connected with the second output end of the transformer TF1 and the second input end of the frequency doubler, and the second end of the inductor L4 is grounded.

6. The W-band low power hexamultiplier for high conversion gain multipliers according to claim 1, wherein the multipliers comprise transistors Q5, Q6, Q7, Q8, Q9, Q10, C7, C8, C9, C10, R5, R6, R7 and R8, wherein:

the first end of the capacitor C7 and the first end of the capacitor C9 are both connected with the first input end of the frequency doubler, the second end of the capacitor C7 is connected with the first end of the resistor R5, the base electrode of the transistor Q7 and the base electrode of the transistor Q10, the second end of the resistor R5 is connected with the bias voltage end Vb3, the second end of the capacitor C9 is connected with the first end of the resistor R7 and the base electrode of the transistor Q5, and the second end of the resistor R7 is connected with the bias voltage end Vb4;

the collector of the transistor Q7 is connected with the collector of the transistor Q9 and the first input end of the output matching network, the emitter of the transistor Q7 is connected with the emitter of the transistor Q8 and the collector of the transistor Q5, the emitter of the transistor Q5 is grounded, the collector of the transistor Q10 is connected with the collector of the transistor Q8 and the second input end of the output matching network, the emitter of the transistor Q10 is connected with the emitter of the transistor Q9 and the collector of the transistor Q6, and the emitter of the transistor Q6 is grounded;

the first end of the capacitor C8 and the first end of the capacitor C10 are both connected with the second input end of the frequency doubler, the second end of the capacitor C8 is connected with the first end of the resistor R6, the base electrode of the transistor Q8 and the base electrode of the transistor Q9, the second end of the capacitor C10 is connected with the first end of the resistor R8 and the base electrode of the transistor Q6, and the second end of the resistor R8 is connected with the bias voltage end Vb4.

7. The W-band low power hexamultiplier for high conversion gain multipliers according to claim 6, wherein the capacitor C7, the capacitor C8, the capacitor C9 and the capacitor C10 each comprise MIM capacitors.

8. The W-band low power hexamultiplier for high conversion gain multipliers of claim 1, wherein the output matching network comprises an output balun BL2, a capacitor C11 and an inductance L5, wherein:

the first input end of the output balun BL2 is connected with the first input end of the output matching network, the second input end of the output balun BL2 is connected with the second input end of the output matching network, the first output end of the output balun BL2 is connected with the first end of the capacitor C11, the second output end of the output balun BL2 is grounded, the second end of the capacitor C11 is connected with the first end of the inductor L5 and the signal output end OUT, and the second end of the inductor L5 is grounded.

9. The W-band low power hexamultiplier for high conversion gain multipliers of claim 8, wherein the capacitor C11 comprises a MIM capacitor.