CN114759879B - Push-based double-tripler - Google Patents
Push-based double-tripler Download PDFInfo
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- CN114759879B CN114759879B CN202210549941.5A CN202210549941A CN114759879B CN 114759879 B CN114759879 B CN 114759879B CN 202210549941 A CN202210549941 A CN 202210549941A CN 114759879 B CN114759879 B CN 114759879B
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- 239000003990 capacitor Substances 0.000 claims abstract description 48
- 238000006386 neutralization reaction Methods 0.000 claims abstract description 28
- 230000005540 biological transmission Effects 0.000 claims description 11
- 238000006243 chemical reaction Methods 0.000 abstract description 9
- 239000000284 extract Substances 0.000 abstract description 4
- 230000001629 suppression Effects 0.000 abstract description 4
- 230000003321 amplification Effects 0.000 abstract description 2
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 2
- 238000004804 winding Methods 0.000 description 11
- 238000004891 communication Methods 0.000 description 5
- 239000000243 solution Substances 0.000 description 4
- 238000000605 extraction Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 230000010355 oscillation Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000001914 filtration Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
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- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B19/00—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source
- H03B19/06—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source by means of discharge device or semiconductor device with more than two electrodes
- H03B19/14—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source by means of discharge device or semiconductor device with more than two electrodes by means of a semiconductor device
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Abstract
The invention provides a push-based double-frequency multiplier, which comprises an NMOS transistor M1, an NMOS transistor M2, a neutralization capacitor Cp1, a neutralization capacitor Cp2 and a transformer TR2; one end of a primary coil of the transformer TR1 is connected with the Port_ I N end, the other end of the primary coil of the transformer TR1 is grounded, one end of a secondary coil of the transformer TR1 is connected with the grid electrode of the NMOS transistor M1 and one end of the neutralization capacitor Cp1, and the other end of the secondary coil of the transformer TR1 is connected with the grid electrode of the NMOS transistor M2 and one end of the neutralization capacitor Cp 2. The invention is based on a push-push structure, and a neutralization capacitor is added at the same time, so that the conversion gain of the frequency multiplier is improved. Meanwhile, a transformer is utilized to distinguish and extract secondary signals and tertiary signals. For the third-order signal, the LB is adopted for buffer amplification, so that the fundamental wave suppression degree of the third-order harmonic signal is improved. And the secondary and tertiary signals are output simultaneously, so that the output bandwidth of the circuit is improved, and the structure reduces the whole plate area and the power consumption.
Description
Technical Field
The invention belongs to the technical field of wireless communication, and particularly relates to a push-based double-tripler.
Background
With the continuous development of wireless communication technology, the operating frequency of the current communication system has begun to be shifted to the terahertz frequency band of radio frequency. Meanwhile, requirements of lower power consumption, higher frequency, larger bandwidth, lower cost and the like are also put forward for the wireless communication system. For one of the core circuits of the transceiver module, the frequency multiplier (Frequency multiplier) can simply and directly increase the output signal frequency of the frequency synthesis module. In addition, in the transmitter, when the frequencies of the local oscillation signals are similar to those of the output signals of the power amplifier, the output signals of the power amplifier can cause interference to the local oscillation signals, and the accuracy of the local oscillation signals is affected. To avoid this, it is necessary to have the frequency of the local oscillator signal differ significantly from the frequency of the signal transmitted by the power amplifier. The frequency multiplier can well realize the function. Therefore, the performance of the frequency multiplier directly affects the accuracy of the high frequency communication system, and faces great demands and challenges. When the frequency multiplication number N of the frequency multiplier is continuously increased, the conversion efficiency is drastically reduced, so that the operating bandwidth is narrowed.
In order to solve the problem of low conversion gain in the frequency doubler, related researchers have proposed an improved frequency doubler circuit, the schematic diagram of which is shown in fig. 1, wherein a differential pair of NMOS transistors generates a second harmonic signal at its output. The capacitors C1 and C2 can transmit the fundamental harmonic signals of the drain terminal to the grid electrode, and frequency multiplication is performed again to generate second harmonic components to improve conversion gain. The transmission lines TL1 and TL2 may extract and filter the second harmonic. The inductance L will match the output of the circuit.
For the scheme of generating the tertiary signal using the nonlinearity of the device, a circuit diagram thereof is shown in fig. 2 as follows. The circuit configuration for generating the tertiary signal by this method can be extremely simple. The third harmonic signal can be generated using only one NMOS transistor M1 operating in Class-a. When the MOS tube is fully conducted and a large signal is input, the output current of the drain end of the MOS tube is close to a square wave, the square wave contains rich odd harmonic current, a third harmonic component is extracted through the LC parallel resonant cavity, and the third harmonic component is shaped into a sine wave signal.
Meanwhile, a structure of a two/three octave of fig. 3 has also been proposed by researchers as follows. Transistors M1 and M2 form a push-push pair to generate a second harmonic signal. Transistors M3 and M4 form a single balance mixer, and the second harmonic wave generated by M1 and M2 and the fundamental wave signal are mixed to obtain a third harmonic wave signal. R1 and R2 are load resistors.
The technical route of the above mentioned two/three frequency doubler is as follows: firstly, adding a differential input signal to a push-push structure to generate a second harmonic signal, directly extracting a part of the second harmonic signal, and outputting the part of the second harmonic signal through a buffer; and directly injecting the other part of second harmonic and differential input signals into a single balance mixer, filtering to obtain third harmonic signals and outputting the third harmonic signals. The double-frequency and triple-frequency device with the structure has the advantages of complex structure, low conversion gain and large circuit occupation area. The specific disadvantages are as follows:
(1) This configuration requires injection of the secondary signal and the differential input signal into the single balanced mixer when generating the third harmonic signal. For a single balanced mixer, the conversion gain is low, which causes larger loss, and meanwhile, the mixer is also an active structure and consumes additional power consumption because the push-push structure is an active structure.
(2) The structure needs to be added with the LC parallel resonant cavity at the position of generating the second harmonic, and the area occupied by the inductor can be large when the frequency is low, so that the area is wasted, and the circuit cost is greatly increased.
Disclosure of Invention
The invention aims to solve the defects in the prior art and provide a push-based double/triple frequency converter circuit, which adopts an improved push-push circuit with a neutralization capacitor to extract different harmonic components from different modes, thereby realizing the function of double/triple frequency conversion. The structure can effectively improve the output bandwidth of the single frequency multiplier, reduce the occupied area and save the cost.
The invention mainly aims to solve the problems of insufficient bandwidth, large occupied area of a chip and high power consumption of the traditional frequency multiplier. For the traditional frequency doubler, a MOS tube pair with a push-push structure is mainly adopted, the phase difference of odd harmonic components in the current at the output end is 180 degrees, the differential signal is used for counteracting, even harmonic is only existed, and then the required second harmonic signal is extracted through the resonant cavity of the drain electrode. This approach is very common but its operating bandwidth is difficult to achieve very large. For the traditional tripler, the nonlinear direct generation and extraction of the third harmonic component of the device can be adopted, so that the function of frequency multiplication is realized. However, this method has very low conversion efficiency, and causes a large amount of power consumption in order to achieve this function; and their Harmonic Rejection Ratio (HRR) is also poor, which can cause significant interference to subsequent circuits, such as mixers. At the same time, the bandwidth of the frequency tripling is difficult to achieve. The invention provides a circuit combining a frequency doubler and a frequency tripler for solving the bandwidth problem. And carrying out odd mode extraction and even mode extraction on the drain current of the push-push pair respectively, and extracting secondary signals and tertiary signals in the drain current. The structure can realize double frequency multiplication and triple frequency multiplication simultaneously, improves the bandwidth of output signals, combines a double frequency multiplication circuit and a triple frequency multiplication circuit, and reduces the area of a chip.
The invention adopts the following technical scheme:
A push-push based frequency doubler. The device comprises three parts, namely a push-push core and a transformer TR2, wherein the push-push core consists of an NMOS transistor M1, an NMOS transistor M2, a neutralization capacitor Cp1 and a neutralization capacitor Cp 2.
One end of a primary coil of the transformer TR1 is connected with the Port_IN end, the other end of the primary coil of the transformer TR1 is grounded, one end of a secondary coil of the transformer TR1 is connected with the grid electrode of the NMOS transistor M1 and one end of the neutralization capacitor Cp1, and the other end of the secondary coil of the transformer TR1 is connected with the grid electrode of the NMOS transistor M2 and one end of the neutralization capacitor Cp 2. The center tap of the transformer TR1 is connected to Vb1. The source electrode of the NMOS transistor M1 is connected with the source electrode of the NMOS transistor and grounded, the drain electrode of the NMOS transistor M1 is connected with the other end of the neutralization capacitor Cp2 and one end of the microwave transmission line TL1, the other end of the microwave transmission line TL1 is connected with one end of the primary winding of the transformer TR2, the drain electrode of the NMOS transistor M5 is connected with the other end of the neutralization capacitor Cp1 and one end of the microwave transmission line TL2, and the other end of the microwave transmission line TL2 is connected with the other end of the primary winding of the transformer TR 2;
The center tap of the primary coil of the transformer TR2 is connected with one end of an inductor L1 and one end of a capacitor C2, the other end of the capacitor C2 is connected with a Vb2, the grid electrode of the NMOS transistor M5 is grounded, the drain electrode of the NMOS transistor M5 is connected with one end of the inductor L2 and one end of a capacitor C3, and the other end of the capacitor C3 is connected with Port_OUT1.
One end of the secondary winding of the transformer TR2 is connected with the drain electrode of the NMOS transistor M3, the grid electrode of the NMOS transistor M4, one end of the capacitor C1 and one end of the secondary winding of the transformer TR 3. The other end of the secondary coil of the transformer TR2 is connected with the grid electrode of the NMOS transistor M3, the drain electrode of the NMOS transistor M4, the other end of the capacitor C1 and the other end of the transformer TR 3.
The source of the NMOS transistor M3 is connected to the source of the NMOS transistor M4 and to ground. The primary winding of the transformer TR3 has one end connected to port_out2 and the other end grounded.
The invention has the beneficial effects that:
the invention is based on a push-push structure, and a neutralization capacitor is added at the same time, so that the conversion gain of the frequency multiplier is improved. Meanwhile, a transformer is utilized to distinguish and extract secondary signals and tertiary signals. And for the third-order signals, ILB is adopted for buffer amplification, so that the fundamental wave suppression system of the third-order harmonic signals is improved. And the secondary and tertiary signals are output simultaneously, so that the output bandwidth of the circuit is improved. This structure reduces overall layout area and power consumption.
Drawings
FIG. 1 is a modified push-push structure frequency doubler;
FIG. 2 is a frequency tripler utilizing the nonlinear characteristics of the device;
FIG. 3 is a two/three frequency multiplier based on the self-mixing principle;
Fig. 4 is a two/three-octave based on a push-push structure.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions in the present invention will be clearly and completely described below, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
As shown in fig. 4, a push-push based frequency tripler of the present invention. The device comprises three parts, namely a push-push core and a transformer TR2, wherein the push-push core consists of an NMOS transistor M1, an NMOS transistor M2, a neutralization capacitor Cp1 and a neutralization capacitor Cp 2.
One end of a primary coil of the transformer TR1 is connected with the Port_IN end, the other end of the primary coil of the transformer TR1 is grounded, one end of a secondary coil of the transformer TR1 is connected with the grid electrode of the NMOS transistor M1 and one end of the neutralization capacitor Cp1, and the other end of the secondary coil of the transformer TR1 is connected with the grid electrode of the NMOS transistor M2 and one end of the neutralization capacitor Cp 2. The center tap of the transformer TR1 is connected to Vb1. The source electrode of the NMOS transistor M1 is connected with the source electrode of the NMOS transistor and grounded, the drain electrode of the NMOS transistor M1 is connected with the other end of the neutralization capacitor Cp2 and one end of the microwave transmission line TL1, the other end of the microwave transmission line TL1 is connected with one end of the primary winding of the transformer TR2, the drain electrode of the NMOS transistor M5 is connected with the other end of the neutralization capacitor Cp1 and one end of the microwave transmission line TL2, and the other end of the microwave transmission line TL2 is connected with the other end of the primary winding of the transformer TR 2;
The center tap of the primary coil of the transformer TR2 is connected with one end of an inductor L1 and one end of a capacitor C2, the other end of the capacitor C2 is connected with a Vb2, the grid electrode of the NMOS transistor M5 is grounded, the drain electrode of the NMOS transistor M5 is connected with one end of the inductor L2 and one end of a capacitor C3, and the other end of the capacitor C3 is connected with Port_OUT1.
One end of the secondary winding of the transformer TR2 is connected with the drain electrode of the NMOS transistor M3, the grid electrode of the NMOS transistor M4, one end of the capacitor C1 and one end of the secondary winding of the transformer TR 3. The other end of the secondary coil of the transformer TR2 is connected with the grid electrode of the NMOS transistor M3, the drain electrode of the NMOS transistor M4, the other end of the capacitor C1 and the other end of the transformer TR 3.
The source of the NMOS transistor M3 is connected to the source of the NMOS transistor M4 and to ground. The primary winding of the transformer TR3 has one end connected to port_out2 and the other end grounded.
The invention can be briefly described as three parts, and the core part is a push-push composed of an NMOS transistor M1, an NMOS transistor M2, a neutralization capacitor Cp1 and a neutralization capacitor Cp 2.
The core part generates a second harmonic signal and a third harmonic signal, which can be extracted by the transformer TR 2.
The second part is a buffer for amplifying the common-mode secondary signal extracted from the center tap of the primary coil of the transformer TR 2.
The third part is ILB that amplifies the differential third harmonic signal extracted from the secondary winding of transformer TR 2. In addition, the transformer TR1 performs input matching for the circuit; the transformer TR3 performs output matching on the ILB, and simultaneously provides a resonant cavity for the ILB, and the inductor L2 and the capacitor C3 perform output matching on the common-source buffer.
This structure can output the secondary frequency signal and the tertiary frequency signal simultaneously. Meanwhile, an Injection-locked buffer (Injection-locked buffer) is adopted for amplifying the extracted third harmonic signal, and meanwhile, the inhibition of fundamental wave signals can be improved. And directly accessing the secondary frequency signal into a common source buffer, amplifying and outputting the amplified secondary frequency signal. The structure has the advantages of higher output bandwidth, smaller area, lower power consumption and the like.
The improved technical characteristics of the invention are as follows:
(1) Push-push pair with added neutralization capacitor and transformer TR2
The invention adds the push-push pair of the neutralization capacitor as a core structure, the structure can generate the needed second harmonic signal and the third harmonic signal, and the efficiency is greatly improved compared with the traditional push-push pair. The transformer TR2 is a structure for extracting and distinguishing the second harmonic signal and the third harmonic signal, and extracts the common mode second signal and the differential mode third signal by using the characteristics of the transformer.
(2) Injection locking buffer
For the third harmonic signal, an injection locking buffer is adopted, so that the third harmonic signal is improved, and meanwhile, the larger fundamental wave signal is subjected to filtering suppression through the resonant cavity, so that the fundamental wave suppression degree of the fundamental wave signal is improved.
(3) Common source stage buffer
The common source stage buffer amplifies the output second harmonic signal.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (1)
1. The push-based double-tripler is characterized by comprising an NMOS transistor M1, an NMOS transistor M2, a neutralization capacitor Cp1, a neutralization capacitor Cp2 and a transformer TR2;
One end of a primary coil of the transformer TR1 is connected with a Port_IN end, the other end of the primary coil of the transformer TR1 is grounded, one end of a secondary coil of the transformer TR1 is connected with a grid electrode of an NMOS transistor M1 and one end of a neutralization capacitor Cp1, the other end of the secondary coil of the transformer TR1 is connected with a grid electrode of an NMOS transistor M2 and one end of a neutralization capacitor Cp2, a center tap of the transformer TR1 is connected with a Vb1, a source electrode of the NMOS transistor M1 is connected with a source electrode of the NMOS transistor and grounded, a drain electrode of the NMOS transistor M1 is connected with the other end of the neutralization capacitor Cp2 and one end of a microwave transmission line TL1, the other end of the microwave transmission line TL2 is connected with the other end of the primary coil of the transformer TR 2;
The center tap of the primary coil of the transformer TR2 is connected with one end of an inductor L1 and one end of a capacitor C2, the other end of the capacitor C2 is connected with a Vb2, the grid electrode of an NMOS transistor M5 is grounded, the drain electrode of the NMOS transistor M5 is connected with one end of the inductor L2 and one end of a capacitor C3, and the other end of the capacitor C3 is connected with Port_OUT1;
One end of the secondary coil of the transformer TR2 is connected with the drain electrode of the NMOS transistor M3, and the grid electrode of the NMOS transistor M4, one end of the capacitor C1 and one end of the secondary coil of the transformer TR 3; the other end of the secondary coil of the transformer TR2 is connected with the grid electrode of the NMOS transistor M3, the drain electrode of the NMOS transistor M4, the other end of the capacitor C1, the other end of the transformer TR3, the source electrode of the NMOS transistor M3 is connected with the source electrode of the NMOS transistor M4 and grounded, one end of the primary coil of the transformer TR3 is connected with Port_OUT2, and the other end is grounded.
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| CN116488587B (en) * | 2023-06-21 | 2023-08-29 | 成都通量科技有限公司 | Double-frequency multiplier based on half-wave rectification superposition |
| CN118249747B (en) * | 2024-05-28 | 2024-09-10 | 西北工业大学 | High harmonic rejection ratio broadband injection locking double-frequency multiplier |
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