CN116317956A - Quadruple frequency device and frequency source - Google Patents
Quadruple frequency device and frequency source Download PDFInfo
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- CN116317956A CN116317956A CN202310103647.6A CN202310103647A CN116317956A CN 116317956 A CN116317956 A CN 116317956A CN 202310103647 A CN202310103647 A CN 202310103647A CN 116317956 A CN116317956 A CN 116317956A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B19/00—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source
- H03B19/06—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source by means of discharge device or semiconductor device with more than two electrodes
- H03B19/14—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source by means of discharge device or semiconductor device with more than two electrodes by means of a semiconductor device
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B1/00—Details
- H03B1/04—Reducing undesired oscillations, e.g. harmonics
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The invention discloses a quad-frequency and a frequency source. The quad-frequency comprises: an input matching network for converting a single-ended input signal to a first differential signal; the first-stage frequency doubling module is used for carrying out frequency doubling output on the first differential signal; the interstage matching network is used for converting the frequency doubling signal into a second differential signal; the second-stage frequency doubling module is used for carrying out frequency doubling output on the second differential signal to generate a quadruple frequency signal; the output matching network is used for amplifying and filtering the quadruple frequency signal; the first-stage frequency doubling module is of a phase control stack double-push frequency doubling structure; and/or the second-stage frequency doubling module is a multi-port driving matching stack double-push frequency doubling structure. The embodiment of the invention improves the coordination capability of broadband and harmonic suppression of the quadrupler.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a quad-frequency device and a frequency source.
Background
High quality satellite communications, point-to-point radio, point-to-multi radio all require local oscillator signals with wide tuning range, low phase noise, and low power to meet the high data rates and wide coverage of Ku and K bands. As a key module in the local oscillator circuit, the performance of the voltage controlled oscillator is inversely proportional to its frequency, and a strict trade-off between bandwidth and phase noise is required to provide a high quality local oscillator signal for the frequency multiplier.
Taking the quad-frequency as an example, in the prior art, its output is relatively narrow band, high-band output is rarely achieved, and 3dB bandwidth is rarely exceeded by 30%. Even if a 3dB bandwidth exceeding 30% can be designed, its harmonic suppression capability will be greatly reduced. Therefore, the prior art has the problem that the wideband and harmonic suppression capabilities of the quadband are difficult to coordinate.
Disclosure of Invention
The invention provides a frequency multiplier and a frequency source so as to improve the coordination capability of broadband and harmonic suppression of the frequency multiplier.
According to an aspect of the present invention, there is provided a quad-frequency comprising:
an input matching network for converting a single-ended input signal to a first differential signal;
the first-stage frequency doubling module is electrically connected with the input matching network and is used for carrying out frequency doubling output on the first differential signal;
the interstage matching network is electrically connected with the first-stage frequency doubling module and is used for converting the frequency doubling signal into a second differential signal;
the second-stage frequency doubling module is electrically connected with the inter-stage matching network and is used for carrying out frequency doubling output on the second differential signal to generate a quadruple frequency signal;
The output matching network is electrically connected with the second-stage frequency doubling module and is used for amplifying and filtering the quadruple frequency signal;
the first-stage frequency doubling module is of a phase control stack double-push frequency doubling structure; and/or the second-stage frequency doubling module is a multi-port driving matching stack double-push frequency doubling structure.
Optionally, the first-stage frequency doubling module includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, and a second capacitor;
the base electrode of the first transistor is used as a first end of the first-stage frequency doubling module and is connected with the normal phase of the first differential signal;
the base electrode of the second transistor is used as the second end of the first-stage frequency doubling module and is connected with the inverted phase of the first differential signal;
the base electrode of the third transistor is connected to the base electrode of the second transistor through the first capacitor, and the base electrode of the third transistor is connected to a bias voltage;
the base electrode of the fourth transistor is connected to the base electrode of the first transistor through the second capacitor, and the base electrode of the fourth transistor is connected to the bias voltage;
The collector of the first transistor is electrically connected with the collector of the second transistor, and outputs the frequency doubling signal;
an emitter of the first transistor is electrically connected to a collector of the third transistor; an emitter of the second transistor is electrically connected with a collector of the fourth transistor;
an emitter of the third transistor and an emitter of the fourth transistor are grounded.
Optionally, the second-stage frequency doubling module includes: a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a third capacitor, a fourth capacitor, a fifth capacitor, and a sixth capacitor;
the base electrode of the fifth transistor is used as a first end of the second-stage frequency doubling module and is connected with the normal phase of the second differential signal;
the base electrode of the sixth transistor is used as the second end of the second-stage frequency doubling module and is connected with the negative phase of the second differential signal;
the base electrode of the seventh transistor is connected to the emitter electrode of the seventh transistor through the fifth capacitor, and the base electrode of the seventh transistor is connected to a bias voltage;
the collector of the seventh transistor is connected to the base of the sixth transistor through the third capacitor;
The base electrode of the eighth transistor is connected to the emitter electrode of the eighth transistor through the sixth capacitor, and the base electrode of the eighth transistor is connected to a bias voltage;
the collector of the eighth transistor is connected to the base of the fifth transistor through the fourth capacitor;
the collector of the fifth transistor is electrically connected with the collector of the sixth transistor, and outputs the quadruple frequency signal;
an emitter of the fifth transistor is electrically connected to a collector of the seventh transistor; an emitter of the sixth transistor is electrically connected to a collector of the eighth transistor;
an emitter of the seventh transistor and an emitter of the eighth transistor are grounded.
Optionally, the bias voltage biases the corresponding transistor in the class AB region.
Optionally, the inter-stage matching network includes: a first amplifying module and a first LC network module;
the first amplification module is electrically connected with the first-stage frequency doubling module and is used for amplifying the frequency doubling signal;
the first LC network module is electrically connected with the first amplifying module and is used for filtering.
Optionally, the first amplifying module includes: a ninth transistor;
The base electrode of the ninth transistor is electrically connected with the first LC network module; the emitter of the ninth transistor is electrically connected with the first-stage frequency doubling module; the collector of the ninth transistor is electrically connected to the first LC network block.
Optionally, the first LC network module includes: a seventh capacitor, an eighth capacitor, a ninth capacitor, a first inductor, a second inductor and a first resistor;
electromagnetic coupling exists between the first inductor and the second inductor;
the first inductor is connected with the eighth capacitor in parallel; the first amplifying module comprises a control end, a first end and a second end; the first end of the first inductor is connected with a power supply voltage, and the second end of the first inductor is electrically connected with the first end of the first amplifying module; the second end of the first amplifying module is electrically connected with the first-stage frequency doubling module;
the first end of the first resistor is electrically connected with the first end of the first inductor; the second end of the first resistor is electrically connected with the first end of the seventh capacitor; the second end of the seventh capacitor is grounded; the second end of the first resistor is electrically connected with the control end of the first amplifying module;
The second inductor is connected with the ninth capacitor in parallel; the first end of the second inductor outputs the normal phase of the second differential signal, the second end of the second inductor outputs the reverse phase of the second differential signal, and the center tap of the second inductor is connected with bias voltage.
Optionally, the output matching network includes: a second amplification module and a second LC network module;
the second amplification module is electrically connected with the second-stage frequency doubling module and is used for amplifying the quadruple frequency signal;
the second LC network module is electrically connected with the second amplifying module and is used for filtering.
Optionally, the second amplifying module includes: a tenth transistor;
the base electrode of the tenth transistor is electrically connected with the second LC network module; the emitter of the tenth transistor is electrically connected with the second-stage frequency doubling module; the collector of the tenth transistor is electrically connected to the second LC network block.
Optionally, the second LC network module includes: a tenth capacitor, an eleventh capacitor, a twelfth capacitor, a third inductor, a fourth inductor and a second resistor;
electromagnetic coupling exists between the third inductor and the fourth inductor;
The third inductor is connected with the eleventh capacitor in parallel; the second LC network module comprises a control end, a first end and a second end; the first end of the third inductor is connected to the power supply voltage, and the second end of the third inductor is electrically connected with the first end of the second amplifying module; the second end of the second amplifying module is electrically connected with the second-stage frequency doubling module;
the first end of the second resistor is electrically connected with the first end of the first inductor; the second end of the second resistor is electrically connected with the first end of the tenth capacitor; the second end of the tenth capacitor is grounded; the second end of the second resistor is electrically connected with the control end of the second amplifying module; the fourth inductor is connected with the twelfth capacitor in parallel; the first end of the twelfth capacitor outputs the quadruple frequency signal; the second end of the twelfth capacitor is grounded.
Optionally, the input matching network includes: thirteenth, fourteenth, fifth and sixth inductances;
electromagnetic coupling exists between the fifth inductor and the sixth inductor;
the fifth inductor is connected with the thirteenth capacitor in parallel; a first end of the thirteenth capacitor is connected to the single-ended input signal, and a second end of the thirteenth capacitor is grounded;
The sixth inductor is connected with the fourteenth capacitor in parallel; the first end of the sixth inductor outputs the normal phase of the first differential signal, the second end of the sixth inductor outputs the reverse phase of the first differential signal, and the center tap of the sixth inductor is connected with the bias voltage.
Optionally, the quad-frequency further comprises: a current mirror; the current mirror is used for providing bias voltage.
Optionally, the current mirror includes: an eleventh transistor, a fifteenth capacitor, a third resistor, and a fourth resistor;
the base electrode of the eleventh transistor outputs the bias voltage through the third resistor, and the second end of the third resistor is used as a bias voltage output end;
the collector electrode of the eleventh transistor is electrically connected with the bias voltage output end; an emitter of the eleventh transistor is grounded;
the fifteenth capacitor is connected between the bias voltage output end and the grounding end;
the fourth resistor is connected between a power supply voltage and a collector of the eleventh transistor.
According to another aspect of the present invention, there is provided a frequency source comprising: the frequency quad as in any of the above embodiments.
The frequency quadrupler provided by the embodiment of the invention adopts a modularized design. The first-stage frequency multiplication module adopts a phase control stack double-push frequency multiplication structure, and harmonic signals generated by the first-stage frequency multiplication module are filtered through an interstage matching network, so that odd harmonic signals in the harmonic signals are reduced, and better fourth harmonic suppression and second harmonic enhancement capability are realized in an ultra-wideband range. The second-stage frequency doubling module adopts a multiport driving matching stack double-push frequency doubling structure, harmonic signals generated by the second-stage frequency doubling module are filtered through an output matching network, and odd harmonic signals in the harmonic signals are filtered again to obtain purer fourth harmonic signals, so that impedance of the second-stage frequency doubling module is reduced, and matching effect of an LC network is improved. In summary, the embodiment of the invention improves the coordination capability of broadband and harmonic suppression of the quad-frequency.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic circuit diagram of a quad-frequency converter according to an embodiment of the present invention;
FIG. 2 is a schematic circuit diagram of another quad-frequency converter provided by an embodiment of the present invention;
FIG. 3 is a schematic circuit diagram of yet another quad-frequency provided by an embodiment of the present invention;
FIG. 4 is a schematic circuit diagram of yet another quad-frequency provided by an embodiment of the present invention;
FIG. 5 is a schematic circuit diagram of yet another quad-frequency provided by an embodiment of the present invention;
FIG. 6 is a schematic circuit diagram of a current mirror according to an embodiment of the present invention;
FIG. 7 is a graph of absolute value of frequency-power versus value of power provided by an embodiment of the present invention;
FIG. 8 is a graph of output power versus DC power consumption versus input power provided by an embodiment of the present invention;
FIG. 9 is a graph of output spectrum versus power at each subharmonic according to an embodiment of the present invention;
FIG. 10 is a schematic circuit diagram of a conventional stack structure provided by an embodiment of the present invention;
FIG. 11 is a schematic circuit diagram of a single multi-port drive architecture provided by an embodiment of the present invention;
FIG. 12 is a schematic circuit diagram of a multi-port drive matching stack double-push frequency multiplication structure according to an embodiment of the present invention;
FIG. 13 is an equivalent diagram of a conventional stack structure provided by an embodiment of the present invention;
FIG. 14 is an equivalent diagram of a single multi-port drive architecture provided by an embodiment of the present invention;
FIG. 15 is an equivalent diagram of a multi-port drive matching stack double-push frequency multiplication structure provided by an embodiment of the present invention;
FIG. 16 is a return loss versus frequency plot of a conventional stack structure, a single multi-port drive structure, and a multi-port drive matching stack double-push frequency multiplication structure provided by an embodiment of the present invention;
fig. 17 is a smith chart of a conventional stack structure, a single-multi-port driving structure, and a multi-port driving matching stack double-push frequency multiplication structure according to an embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The embodiment of the invention provides a frequency multiplier which can be applied to communication modes such as satellite communication, radio communication and the like and provides signals with a wide tuning range for the satellite communication and the radio communication. Fig. 1 is a schematic circuit diagram of a quad-frequency converter according to an embodiment of the present invention. Referring to fig. 1, the quad-register includes:
An input matching network 110, the input matching network 110 being configured to convert a single-ended input signal into a first differential signal;
the first-stage frequency doubling module 120, the first-stage frequency doubling module 120 is electrically connected with the input matching network 110, and is used for performing frequency doubling output on the first differential signal;
the interstage matching network 130 is electrically connected with the first-stage frequency doubling module 120 and is used for converting the frequency doubling signal into a second differential signal;
the second-stage frequency doubling module 140, the second-stage frequency doubling module 140 is electrically connected with the inter-stage matching network 130, and is used for performing frequency doubling output on the second differential signal to generate a quadruple frequency signal;
the output matching network 150 is electrically connected with the second-stage frequency doubling module 140 and is used for amplifying and filtering the quadruple frequency signal;
the first-stage frequency doubling module 120 is a phase control stack double-push frequency doubling structure; and/or, the second-stage frequency doubling module 140 is a multi-port driving matching stack double-push frequency doubling structure.
It is understood that the single-ended input signal, i.e., the input signal to the matching network 110, is a single-ended signal, as opposed to a differential signal. Differential signals are distinguished from single-ended signals, which means that a signal has a transmission signal in both transmission lines, and that the signals in both transmission lines are equal in amplitude and opposite in phase.
Illustratively, the input matching network 110 has a balun structure therein. The balun is a three-port device, and is based on the application of a transformer, and can output a constant-amplitude reverse signal, so that a single-ended input signal is converted into a differential signal. The differential signal output from the input matching network 110 is a first differential signal.
The first-stage frequency multiplication module 120 receives the first differential signal sent by the input matching network 110, and uses the first differential signal as a fundamental wave signal, so as to generate rich harmonic signals based on the first differential signal. The harmonic signals generated by the first stage multiplier 120 include various harmonic signals, such as second harmonic, third harmonic, fourth harmonic, fifth harmonic, etc.; but only the second harmonic is the desired harmonic signal. The first-stage frequency doubling module 120 is a phase control stack double-push frequency doubling structure, which is used for reverse modulation and signal amplification of harmonic signals, so that the first-stage frequency doubling module 120 can strengthen the harmonic signals and amplify the harmonic signals. Since the sum of the energies of the harmonic signals generated by the first stage multiplier 120 is constant, when one or more of the harmonic signals are attenuated, the harmonic signals that are not attenuated are emphasized. Illustratively, among the harmonic signals, the fourth harmonic signal is easier to control than the remaining harmonic signals, and the first-stage frequency doubling module 120 may suppress the generated fourth harmonic signal, thereby enhancing the second harmonic signal. In this process, the first stage doubler 120 converts the differential signal to a single-ended signal for output to the inter-stage matching network 130.
The inter-stage matching network 130 receives the single-ended signal sent by the first stage doubling module 120 and filters the single-ended signal, thereby reducing the odd harmonic signal output to the second stage doubling module 140. The structure of the inter-stage matching network 130 is similar to that of the input matching network 110, and the structure of the inter-stage matching network 130 is not repeated, and the inter-stage matching network 130 converts the single-ended signal sent by the first-stage frequency doubler 120 into a second differential signal and sends the second differential signal to the second-stage frequency doubler module 140.
The second-stage frequency doubling module 140 receives the second differential signal sent by the inter-stage matching network 130, and uses the second differential signal as a fundamental wave signal, so as to generate a fourth harmonic signal based on the second differential signal. Unlike the first-stage frequency doubling module 120, the inter-stage matching network 130 filters the odd harmonic signals, so that the second differential signal input to the second-stage frequency doubling module 140 is basically a second harmonic signal, and therefore, the harmonic signals generated by the second-stage frequency doubling module 140 are mostly fourth harmonic signals. It should be noted that, the second-stage frequency doubling module 140 is a multi-port driving matching stack frequency doubling structure, which can reduce the impedance of the second-stage frequency doubling module 140, and has an amplifier structure in the structure, so as to amplify the harmonic signal. The second-stage frequency doubling module 140 amplifies the generated harmonic signal and converts the amplified harmonic signal into a single-ended signal to output to the output matching network 150.
The output matching network 150 receives the single-ended signal sent by the second-stage frequency doubling module 140, and filters the single-ended signal, thereby reducing the odd harmonic signal included in the harmonic signal, and outputting a purer fourth harmonic signal.
The frequency quadrupler provided by the embodiment of the invention adopts a modularized design. The first-stage frequency multiplication module 120 adopts a phase control stack double-push frequency multiplication structure, and filters harmonic signals generated by the first-stage frequency multiplication module 120 through the inter-stage matching network 130, so as to reduce odd harmonic signals in the harmonic signals, thereby being beneficial to realizing better fourth harmonic suppression and second harmonic enhancement capability in an ultra-wideband range. The second-stage frequency doubling module 140 adopts a multi-port driving matching stack double-push frequency doubling structure, and the harmonic signals generated by the second-stage frequency doubling module 150 are filtered through the output matching network 150, so that odd harmonic signals in the harmonic signals are filtered again, and purer fourth harmonic signals are obtained, so that the impedance of the second-stage frequency doubling module 140 is reduced, and the matching effect of the LC network is improved. In summary, the embodiment of the invention improves the coordination capability of broadband and harmonic suppression of the quad-frequency.
Fig. 2 is a schematic circuit diagram of another quad-frequency converter according to an embodiment of the present invention. Optionally, based on the above embodiment, referring to fig. 2, the inter-stage matching network 130 includes: a first amplifying module 131 and a first LC network module 132; the first amplifying module 131 is electrically connected with the first-stage frequency doubling module 120, and the first amplifying module 131 is used for amplifying the frequency doubling signal; the first LC network module 132 is electrically connected to the first amplifying module 131, and the first LC network module 132 is used for filtering.
Specifically, the first-stage frequency doubling module 120 inputs the converted single-ended signal to the first amplifying module 131, the first amplifying module 131 amplifies the single-ended signal, then the amplified single-ended signal is transmitted to the first LC network module 132, the first LC network module 132 filters the single-ended signal to reduce odd harmonic signals in the single-ended signal, and the filtered single-ended signal is output to the second-stage frequency doubling module 140.
Optionally, with continued reference to fig. 2 based on the above embodiment, the output matching network 150 includes: a second amplification module 151 and a second LC network module 152; the second amplifying module 151 is electrically connected with the second-stage frequency doubling module 140, and the second amplifying module 151 is used for amplifying the quadruple frequency signal; the second LC network module 152 is electrically connected to the second amplifying module 151, and the second LC network module 152 is used for filtering.
Specifically, the second-stage frequency doubling module 140 inputs the converted single-ended signal into the second amplifying module 151, the second amplifying module 151 amplifies the single-ended signal, and then the amplified single-ended signal is transmitted into the second LC network module 152, and the second LC network module 152 filters the single-ended signal to reduce odd harmonic signals in the single-ended signal and outputs the filtered single-ended signal.
Optionally, with continued reference to fig. 2, based on the above embodiment, the first amplifying module 131 includes: a ninth transistor Q9; the base of the ninth transistor Q9 is electrically connected to the first LC network block 132; the emitter of the ninth transistor Q9 is electrically connected with the first-stage frequency doubling module 120; the collector of the ninth transistor Q9 is electrically connected to the first LC network block 132. The first amplifying module 131 is thus designed to be simple in structure and easy to implement.
Optionally, with continued reference to fig. 2 based on the above embodiment, the first LC network module 132 includes: a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, a first inductor L1, a second inductor L2, and a first resistor R1; electromagnetic coupling exists between the first inductor L6 and the second inductor L2; the first inductor L1 is connected with the eighth capacitor C8 in parallel; the first amplifying module 131 includes a control end, a first end, and a second end; a first end of the first inductor L1 is connected to a power supply voltage, and a second end of the first inductor L1 is electrically connected with a first end of the first amplifying module 131; the second end of the first amplifying module 131 is electrically connected with the first-stage frequency doubling module 120; the first end of the first resistor R1 is electrically connected with the first end of the first inductor L1; the second end of the first resistor R1 is electrically connected with the first end of the seventh capacitor C7; the second end of the seventh capacitor C7 is grounded; the second end of the first resistor R1 is electrically connected with the control end of the first amplifying module 131; the second inductor L2 is connected in parallel with the ninth capacitor C9; the first end of the second inductor L1 outputs the normal phase of the second differential signal, the second end of the second inductor L2 outputs the reverse phase of the second differential signal, and the center tap of the second inductor L2 is connected with the bias voltage.
Optionally, with continued reference to fig. 2, based on the above embodiment, the second amplifying module 151 includes: a tenth transistor Q10; the base of the tenth transistor Q10 is electrically connected to the second LC network block 152; the emitter of the tenth transistor Q10 is electrically connected to the second-stage frequency doubling module 140; the collector of the tenth transistor Q10 is electrically connected to the second LC network block 152. The second amplifying module 151 is thus designed to be simple in structure and easy to implement.
Optionally, with continued reference to fig. 2 based on the above embodiments, the second LC network module 152 includes: a tenth capacitor C10, an eleventh capacitor C11, a twelfth capacitor C12, a third inductor L3, a fourth inductor L4, and a second resistor R2; electromagnetic coupling exists between the third inductor L3 and the fourth inductor L4; the third inductor L3 is connected in parallel with the eleventh capacitor C11; the second LC network module 152 includes a control end, a first end, and a second end; the first end of the third inductor L3 is connected to the power supply voltage, and the second end of the third inductor L3 is electrically connected with the first end of the second amplifying module 152; a second end of the second amplifying module 152 is electrically connected to the second-stage frequency doubling module 140; the first end of the second resistor R2 is electrically connected with the first end of the first inductor L1; the second end of the second resistor R2 is electrically connected with the first end of the tenth capacitor C10; the second end of the tenth capacitor C10 is grounded; a second end of the second resistor R1 is electrically connected to the control end of the second amplifying module 151; the fourth inductor L4 is connected in parallel with the twelfth capacitor C12; the first end of the twelfth capacitor C12 outputs a quadruple frequency signal; the second terminal of the twelfth capacitor C12 is grounded.
Fig. 3 is a schematic circuit diagram of yet another quad-frequency converter according to an embodiment of the present invention. Optionally, based on the above embodiment, referring to fig. 3, the first stage frequency doubling module 120 includes: the first transistor Q1, the second transistor Q2, the third transistor Q3, the fourth transistor Q4, the first capacitor C1, and the second capacitor C2.
The base of the first transistor Q1 is used as a first end of the first-stage frequency doubling module 120, and is connected to the normal phase of the first differential signal; the base electrode of the second transistor Q2 is used as the second end of the first-stage frequency doubling module 120, and is connected with the phase inversion of the first differential signal; the base electrode of the Q3 of the third transistor is connected to the base electrode of the second transistor Q2 through a first capacitor C1, and the base electrode of the third transistor Q3 is connected to a bias voltage; the base electrode of the fourth transistor Q4 is connected to the base electrode of the first transistor Q1 through a second capacitor C2, and the base electrode of the fourth transistor Q4 is connected to the bias voltage; the collector of the first transistor Q1 is electrically connected with the collector of the second transistor Q2, and outputs a frequency doubling signal; an emitter of the first transistor Q1 is electrically connected to a collector of the third transistor Q3; an emitter of the second transistor Q2 is electrically connected to a collector of the fourth transistor Q4; an emitter of the third transistor Q3 and an emitter of the fourth transistor Q4 are grounded.
Specifically, the positive phase and the negative phase of the first differential signal are opposite phases to each other. It will be appreciated that here the positive phase and the negative phase are relatively speaking, i.e. the phases of the signals are symmetrical to each other, the positive phase and the negative phase depending on the chosen reference phase. Therefore, the positive phase may also be referred to as an inverted phase, and the inverted phase may also be referred to as a positive phase.
The first transistor Q1, the second transistor Q2, the third transistor Q3, the fourth transistor Q4, the first capacitor C1 and the second capacitor C2 form a phase control stack double-push frequency multiplication structure of the first stage double frequency multiplication module 120. The first differential signal output from the input matching network 110 is injected into the base of the first transistor Q1 and the base of the second transistor Q2, and a rich harmonic signal is generated at the collector of the third transistor Q3 and the collector of the fourth transistor Q4 by using the nonlinear characteristics of the transistors. The first transistor Q1 and the second transistor Q2 form a common collector amplifier, the third transistor Q3 and the fourth transistor Q4 form a common emitter amplifier, and the arrangement of the structure can realize good balance among harmonic suppression, output power and power consumption while amplifying a required signal. It is understood that the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 are all driven to operate by bias voltages. The common emitter amplifier is reversely modulated under the drive of the common collector amplifier, and even harmonic signals are enhanced under the modulation; and, the positive phase signal of the first differential signal is connected to the base electrode of the fourth transistor Q4 through the second capacitor C2, and the negative phase signal of the first differential signal is connected to the base electrode of the third transistor Q3 through the first capacitor C1, so as to reduce the fourth harmonic signal in the harmonic signals and improve the working efficiency of the first-stage frequency doubling module 120.
Fig. 4 is a schematic circuit diagram of yet another quad-frequency converter provided by an embodiment of the present invention. Optionally, based on the above embodiment, referring to fig. 4, the second stage frequency doubling module 140 includes: the fifth transistor Q5, the sixth transistor Q6, the seventh transistor Q7, the eighth transistor Q8, the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, and the sixth capacitor C6.
The base electrode of the fifth transistor Q5 is used as the first end of the second-stage frequency doubling module 140, and is connected with the normal phase of the second differential signal; the base electrode of the sixth transistor Q6 is used as the second end of the second-stage frequency doubling module 140, and is connected with the negative phase of the second differential signal; the base electrode of the seventh transistor Q7 is connected to the emitter electrode of the seventh transistor Q7 through a fifth capacitor C5, and the base electrode of the seventh transistor Q7 is connected to the bias voltage; the collector of the seventh transistor Q7 is connected to the base of the sixth transistor Q6 through a third capacitor C3; the base electrode of the eighth transistor Q8 is connected to the emitter electrode of the eighth transistor Q8 through a sixth capacitor C6, and the base electrode of the eighth transistor Q8 is connected to a bias voltage; the collector of the eighth transistor Q8 is connected to the base of the fifth transistor Q5 through a fourth capacitor C4; the collector of the fifth transistor Q5 is electrically connected with the collector of the sixth transistor Q6 and outputs a quadruple frequency signal; an emitter of the fifth transistor Q5 is electrically connected to a collector of the seventh transistor Q7; an emitter of the sixth transistor Q6 is electrically connected to a collector of the eighth transistor Q8; the emitter of the seventh transistor Q7 and the emitter of the eighth transistor Q8 are grounded.
The fifth transistor Q5, the sixth transistor Q6, the seventh transistor Q7, the eighth transistor Q8, the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5 and the sixth capacitor C6 form a multi-port driving matching stack double-push frequency multiplication structure of the second stage double frequency multiplication module 140. Specifically, the inter-stage matching network 130 injects the second differential signal into the base of the fifth transistor Q5 and the base of the sixth transistor Q6, again utilizing the non-linear characteristics of the transistors to generate fourth harmonic signals at the collector of the seventh transistor Q7 and the collector of the eighth transistor Q8. It should be noted that, since the first-stage frequency doubling module 120 strengthens the second harmonic signal, the inter-stage matching network 130 filters most of the odd harmonic signals, and thus the second differential signals input to the second-stage frequency doubling module 140 are all basically the second harmonic signals. The capacitor arrangement in the second stage doubling module 140 is different from that of the first stage doubling module 120. Unlike the first-stage frequency doubling module 120, the third capacitor C3 and the fourth capacitor C4 are port driving capacitors, the capacitors can be regarded as resistors in the high-frequency circuit, and the third capacitor C3 and the fourth capacitor C4 are equivalent to resistors, that is, a resistor is connected in parallel to the base of the transistor, so that the input impedance of the base of the transistor is reduced, the impedance of the second-stage frequency doubling module 140 is further reduced, the difficulty in impedance matching of the second-stage frequency doubling module 140 is reduced, and the broadband design of the inter-stage matching network is facilitated. Compared with a conventional stack structure and a single-multiport driving structure, the multiport driving matching stack double-push frequency multiplication structure can achieve better impedance matching effect and smaller volume.
Alternatively, based on the above embodiments, the bias voltage biases the corresponding transistor in the class AB region.
Specifically, the class AB region is related to the on-voltage of the transistor, and the class AB region is located at a value near the voltage value of the on-voltage of the transistor. In an embodiment of the invention, each transistor controlled by the bias voltage operates in the class AB region.
Fig. 5 is a schematic circuit diagram of yet another quad-frequency converter provided by an embodiment of the present invention. Optionally, based on the above embodiment, referring to fig. 5, the input matching network 110 includes: thirteenth capacitor C13, fourteenth capacitor C14, fifth inductor L5, and sixth inductor L6.
Electromagnetic coupling exists between the fifth inductor L5 and the sixth inductor L6; the fifth inductance L5 is connected in parallel with the thirteenth capacitance C13; a first end of the thirteenth capacitor C13 is connected to the single-ended input signal, and a second end of the thirteenth capacitor C13 is grounded; the sixth inductor L6 is connected in parallel with the fourteenth capacitor C14; the first end of the sixth inductor L6 outputs the normal phase of the first differential signal, the second end of the sixth inductor L6 outputs the reverse phase of the first differential signal, and the center tap of the sixth inductor L6 is connected with the bias voltage.
Specifically, the fifth inductor L5 and the sixth inductor L6 form a transformer, the coupling coefficient of the two is k1, and the transformer, the thirteenth capacitor C13 and the fourteenth capacitor C14 form a balun structure to convert the matched input into the differential output.
Optionally, on the basis of the above embodiment, the quad-frequency further includes: a current mirror; the current mirror is used to provide a bias voltage.
Fig. 6 is a schematic circuit diagram of a current mirror according to an embodiment of the present invention. Alternatively, on the basis of the above embodiment, referring to fig. 17, the current mirror includes: an eleventh transistor Q11, a fifteenth capacitor C15, a third resistor R3, and a fourth resistor R4.
The base electrode of the eleventh transistor Q11 outputs bias voltage through a third resistor R3, and the second end of the third resistor R3 is used as a bias voltage output end; the collector of the eleventh transistor Q11 is electrically connected to the bias voltage output terminal; an emitter of the eleventh transistor Q11 is grounded; the fifteenth capacitor C15 is connected between the bias voltage output terminal and the ground terminal; the fourth resistor R4 is connected between the power supply voltage and the collector of the eleventh transistor Q11. The current mirror is simple in structure and easy to realize.
Based on the above embodiments, simulation verification and principle explanation are performed by taking the circuit configuration shown in fig. 5 as an example.
Fig. 7 is a graph of absolute value of frequency-power versus power provided by an embodiment of the present invention. In connection with fig. 7, it is clear that with a fixed input power (pin=2 dBm), the output power remains within a variation range of 3dB, i.e. 37.4% of the central bandwidth, between 14.8-21.6 GHz. The worst case harmonic rejection is 22.1dBc at the second order harmonic, 44.4dBc at the base harmonic, and 35.7dBc at the third order harmonic over the entire operating bandwidth. Wherein f is shown in FIG. 7 0 Is the fundamental frequency.
Fig. 8 is a graph of output power versus dc power consumption versus input power according to an embodiment of the present invention. Referring to fig. 8, it can be seen that the quad-converter of this embodiment has a saturated output of-0.87 dBm and a power of 51mW at 17.6 GHz.
Fig. 9 is a diagram of output spectrum and power of each subharmonic according to an embodiment of the present invention. Referring to fig. 9, it can be seen that the quad-converter of the present embodiment can achieve suppression of greater than 23.9dBc at the sixth harmonic.
In order to better embody the technical advantages of the multi-port driving matching stack double-push frequency multiplication structure, the embodiment compares the multi-port driving matching stack double-push frequency multiplication structure with a conventional stack structure and a single multi-port driving structure. Fig. 10 is a schematic circuit diagram of a conventional stack structure provided by an embodiment of the present invention. Fig. 11 is a schematic circuit diagram of a single multi-port driving structure according to an embodiment of the present invention. Fig. 12 is a schematic circuit diagram of a multi-port driving matching stack double-push frequency multiplication structure according to an embodiment of the present invention. Fig. 13 is an equivalent diagram of a conventional stack structure provided by an embodiment of the present invention. Fig. 14 is an equivalent diagram of a single multi-port driving structure provided by an embodiment of the present invention. Fig. 15 is an equivalent diagram of a multi-port driving matching stack double-push frequency multiplication structure according to an embodiment of the present invention. Fig. 16 is a return loss versus frequency plot for a conventional stack structure, a single multi-port drive structure, and a multi-port drive matching stack double-push frequency multiplication structure provided by an embodiment of the present invention. Fig. 17 is a smith chart of a conventional stack structure, a single-multi-port driving structure, and a multi-port driving matching stack double-push frequency multiplication structure according to an embodiment of the present invention.
With reference to fig. 10-16, the input impedance Z of the conventional stack structure in1 Input impedance Z of single multiport driving structure in2 Input impedance Z of multi-port drive matching stack double-push frequency multiplication structure in3 The corresponding return loss at different frequencies can be seen in fig. 16, and according to the curve shown in fig. 16, it can be seen that the return loss of the conventional stack structure is higher than-10 dB with the return loss of the single-multiport driving structure, and the return loss of the multiport driving matching stack double-push frequency multiplication structure is lower than-10 dB, so that the impedance matching effect of the conventional stack structure and the single-multiport driving structure is poor compared with the impedance matching effect of the multiport driving matching stack double-push frequency multiplication structure. As can also be seen in the smith chart in combination with fig. 13-16 and 17, the equivalent impedance Z of the conventional stack structure L1 Equivalent impedance Z of single multiport driving structure L2 Equivalent impedance Z of the double-push frequency multiplication structure is also compared with that of the multi-port drive matching stack L3 High. The Smith chart is shown inThe reflection system is plotted on the scattered plane with a calculation chart of normalized input impedance equivalence circle, which is mainly used for impedance matching of transmission lines. In short, the closer the center of the curve on the smith chart is to the center of the smith chart, the smaller the impedance value represented by the curve is, and the better the impedance matching effect is. Therefore, it can be seen that the equivalent impedance Z corresponding to the multi-port drive matching stack double-push frequency multiplication structure L3 Equivalent impedance Z lower than conventional stack structure L1 Equivalent impedance Z of single multi-port drive structure L2 The impedance matching effect of the multi-port driving matching stack double-push frequency multiplication structure is better than that of the conventional stack structure and the single-multi-port driving structure.
Referring to fig. 10-12, the circuit of the conventional stack structure, the circuit of the single-multi-port driving structure and the circuit of the multi-port driving matching stack double-push frequency multiplication structure are respectively substituted into simulation calculation software, the size of the seventh inductor L7 of the conventional stack structure is 720pH, the size of the ninth inductor L9 of the single-multi-port driving structure is 600pH, and the size of the twelfth inductor L12 of the multi-port driving matching stack double-push frequency multiplication structure is 382pH. The inductance values of the seventh inductance L7 and the ninth inductance L9 are larger than the inductance value of the twelfth inductance L12. Since the volume of the inductor is proportional to the inductance value of the inductor, the larger the inductance value of the inductor is, the larger the volume of the inductor is, that is, the volume of the seventh inductor L7 and the ninth inductor L9 is larger than the twelfth inductor L12. Therefore, it can be known that the multi-port driving matching stack double-push frequency multiplication structure has better impedance matching effect than the two structures, and the volume of the multi-port driving matching stack double-push frequency multiplication structure is also lower than the two structures. According to the embodiment, the inductance value in the stack structure is calculated through simulation calculation, so that the impedance matching effect is ensured, and meanwhile, the volume of the inductance is reduced. The second-stage frequency doubling module 140 of the embodiment adopts a multi-port driving matching stack double-push frequency doubling structure, and calculates the inductance value in the multi-port driving matching stack double-push structure through simulation calculation, so that the volume of the inductance is reduced while the impedance matching effect is ensured.
The frequency quadrupler provided by the embodiment of the invention adopts a modularized design. The first-stage frequency multiplication module 120 adopts a phase control stack double-push frequency multiplication structure, and a method of combining a phase control capacitor with a transistor base is adopted, so that better fourth harmonic suppression and second harmonic enhancement capability are realized in an ultra-wideband range. The second-stage frequency doubling module 140 adopts a multi-port driving matching stack double-push frequency doubling structure, and the impedance of the second-stage frequency doubling module 140 is reduced by combining a port matching capacitor with a transistor collector, so that the matching effect of an LC network is improved. And the second-stage frequency doubling module 140 can reduce the volume of the inductor while ensuring the impedance matching effect. In addition, the special structural designs of the first amplifying module 131 and the second amplifying module 151 can amplify the required signals while enhancing the harmonic suppression capability, and achieve good trade-offs in harmonic suppression, output power, and power consumption.
The embodiment of the invention also provides a frequency source. The frequency source includes: the quad provided in any of the embodiments above. The frequency source provided in this embodiment has the beneficial effects of the frequency quadrupler provided in any of the above embodiments, and will not be described herein.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.
The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.
Claims (14)
1. A quad-frequency device, comprising:
an input matching network for converting a single-ended input signal to a first differential signal;
the first-stage frequency doubling module is electrically connected with the input matching network and is used for carrying out frequency doubling output on the first differential signal;
the interstage matching network is electrically connected with the first-stage frequency doubling module and is used for converting the frequency doubling signal into a second differential signal;
The second-stage frequency doubling module is electrically connected with the inter-stage matching network and is used for carrying out frequency doubling output on the second differential signal to generate a quadruple frequency signal;
the output matching network is electrically connected with the second-stage frequency doubling module and is used for amplifying and filtering the quadruple frequency signal;
the first-stage frequency doubling module is of a phase control stack double-push frequency doubling structure; and/or the second-stage frequency doubling module is a multi-port driving matching stack double-push frequency doubling structure.
2. The quad of claim 1, wherein the first stage frequency doubling module comprises: a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, and a second capacitor;
the base electrode of the first transistor is used as a first end of the first-stage frequency doubling module and is connected with the normal phase of the first differential signal;
the base electrode of the second transistor is used as the second end of the first-stage frequency doubling module and is connected with the inverted phase of the first differential signal;
the base electrode of the third transistor is connected to the base electrode of the second transistor through the first capacitor, and the base electrode of the third transistor is connected to a bias voltage;
The base electrode of the fourth transistor is connected to the base electrode of the first transistor through the second capacitor, and the base electrode of the fourth transistor is connected to the bias voltage;
the collector of the first transistor is electrically connected with the collector of the second transistor, and outputs the frequency doubling signal;
an emitter of the first transistor is electrically connected to a collector of the third transistor; an emitter of the second transistor is electrically connected with a collector of the fourth transistor;
an emitter of the third transistor and an emitter of the fourth transistor are grounded.
3. The quad of claim 1, wherein the second stage frequency doubling module comprises: a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a third capacitor, a fourth capacitor, a fifth capacitor, and a sixth capacitor;
the base electrode of the fifth transistor is used as a first end of the second-stage frequency doubling module and is connected with the normal phase of the second differential signal;
the base electrode of the sixth transistor is used as the second end of the second-stage frequency doubling module and is connected with the negative phase of the second differential signal;
the base electrode of the seventh transistor is connected to the emitter electrode of the seventh transistor through the fifth capacitor, and the base electrode of the seventh transistor is connected to a bias voltage;
The collector of the seventh transistor is connected to the base of the sixth transistor through the third capacitor;
the base electrode of the eighth transistor is connected to the emitter electrode of the eighth transistor through the sixth capacitor, and the base electrode of the eighth transistor is connected to a bias voltage;
the collector of the eighth transistor is connected to the base of the fifth transistor through the fourth capacitor;
the collector of the fifth transistor is electrically connected with the collector of the sixth transistor, and outputs the quadruple frequency signal;
an emitter of the fifth transistor is electrically connected to a collector of the seventh transistor; an emitter of the sixth transistor is electrically connected to a collector of the eighth transistor;
an emitter of the seventh transistor and an emitter of the eighth transistor are grounded.
4. A quad-frequency according to claim 2 or 3, wherein the bias voltage biases the corresponding transistor in the class AB region.
5. The quad of claim 1, wherein the inter-stage matching network comprises: a first amplifying module and a first LC network module;
the first amplification module is electrically connected with the first-stage frequency doubling module and is used for amplifying the frequency doubling signal;
The first LC network module is electrically connected with the first amplifying module and is used for filtering.
6. The quad of claim 5, wherein the first amplification module comprises: a ninth transistor;
the base electrode of the ninth transistor is electrically connected with the first LC network module; the emitter of the ninth transistor is electrically connected with the first-stage frequency doubling module; the collector of the ninth transistor is electrically connected to the first LC network block.
7. The quad of claim 5, wherein the first LC network module comprises: a seventh capacitor, an eighth capacitor, a ninth capacitor, a first inductor, a second inductor and a first resistor;
electromagnetic coupling exists between the first inductor and the second inductor;
the first inductor is connected with the eighth capacitor in parallel; the first amplifying module comprises a control end, a first end and a second end; the first end of the first inductor is connected with a power supply voltage, and the second end of the first inductor is electrically connected with the first end of the first amplifying module; the second end of the first amplifying module is electrically connected with the first-stage frequency doubling module;
The first end of the first resistor is electrically connected with the first end of the first inductor; the second end of the first resistor is electrically connected with the first end of the seventh capacitor; the second end of the seventh capacitor is grounded; the second end of the first resistor is electrically connected with the control end of the first amplifying module;
the second inductor is connected with the ninth capacitor in parallel; the first end of the second inductor outputs the normal phase of the second differential signal, the second end of the second inductor outputs the reverse phase of the second differential signal, and the center tap of the second inductor is connected with bias voltage.
8. The quad of claim 1, wherein the output matching network comprises: a second amplification module and a second LC network module;
the second amplification module is electrically connected with the second-stage frequency doubling module and is used for amplifying the quadruple frequency signal;
the second LC network module is electrically connected with the second amplifying module and is used for filtering.
9. The quad of claim 8, wherein the second amplification module comprises: a tenth transistor;
The base electrode of the tenth transistor is electrically connected with the second LC network module; the emitter of the tenth transistor is electrically connected with the second-stage frequency doubling module; the collector of the tenth transistor is electrically connected to the second LC network block.
10. The quad of claim 8, wherein the second LC network module comprises: a tenth capacitor, an eleventh capacitor, a twelfth capacitor, a third inductor, a fourth inductor and a second resistor;
electromagnetic coupling exists between the third inductor and the fourth inductor;
the third inductor is connected with the eleventh capacitor in parallel; the second LC network module comprises a control end, a first end and a second end; the first end of the third inductor is connected to the power supply voltage, and the second end of the third inductor is electrically connected with the first end of the second amplifying module; the second end of the second amplifying module is electrically connected with the second-stage frequency doubling module;
the first end of the second resistor is electrically connected with the first end of the first inductor; the second end of the second resistor is electrically connected with the first end of the tenth capacitor; the second end of the tenth capacitor is grounded; the second end of the second resistor is electrically connected with the control end of the second amplifying module; the fourth inductor is connected with the twelfth capacitor in parallel; the first end of the twelfth capacitor outputs the quadruple frequency signal; the second end of the twelfth capacitor is grounded.
11. The quad of claim 1, wherein the input matching network comprises: thirteenth, fourteenth, fifth and sixth inductances;
electromagnetic coupling exists between the fifth inductor and the sixth inductor;
the fifth inductor is connected with the thirteenth capacitor in parallel; a first end of the thirteenth capacitor is connected to the single-ended input signal, and a second end of the thirteenth capacitor is grounded;
the sixth inductor is connected with the fourteenth capacitor in parallel; the first end of the sixth inductor outputs the normal phase of the first differential signal, the second end of the sixth inductor outputs the reverse phase of the first differential signal, and the center tap of the sixth inductor is connected with the bias voltage.
12. The quad of claim 1, further comprising: a current mirror; the current mirror is used for providing bias voltage.
13. The quad of claim 11, wherein the current mirror comprises: an eleventh transistor, a fifteenth capacitor, a third resistor, and a fourth resistor;
the base electrode of the eleventh transistor outputs the bias voltage through the third resistor, and the second end of the third resistor is used as a bias voltage output end;
The collector electrode of the eleventh transistor is electrically connected with the bias voltage output end; an emitter of the eleventh transistor is grounded;
the fifteenth capacitor is connected between the bias voltage output end and the grounding end;
the fourth resistor is connected between a power supply voltage and a collector of the eleventh transistor.
14. A frequency source, comprising: the quad-frequency device of any of claims 1-13.
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| CN117559916A (en) * | 2023-10-30 | 2024-02-13 | 隔空微电子(深圳)有限公司 | Frequency multiplier circuit, frequency multiplier, communication system and frequency multiplier circuit arrangement structure |
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