WO2016041575A1

WO2016041575A1 - A power efficient frequency multiplier

Info

Publication number: WO2016041575A1
Application number: PCT/EP2014/069662
Authority: WO
Inventors: Mingquan Bao
Original assignee: Telefonaktiebolaget L M Ericsson (Publ)
Priority date: 2014-09-16
Filing date: 2014-09-16
Publication date: 2016-03-24

Abstract

A frequency multiplier (100; 200) for generating an output signal with a specific frequency from an input signal is disclosed. The frequency multiplier (100; 200) comprises a first stage (101; 201) which is an even-order harmonic generator to produce a 2nd, a 4th, a 6th, a 8th... order harmonics of the input signal. The frequency multiplier (100; 200) further comprises a second stage (102; 202) which is a nonlinear converter configured to receive the generated even-order harmonics and generate signals with the specific frequency by multiplying, mixing and amplifying the received even-order harmonics. The second stage (102; 202) further combines the generated signals to generate the output signal with a specific frequency. Further, there is a transformer (103; 203) connected between the first and second stages, and also a high pass or band pass filter (104; 204) at the output of the frequency multiplier (100; 200) to supress signals with undesired frequency.

Description

A POWER EFFICIENT FREQUENCY MULTIPLIER

TECHNICAL FIELD

Embodiments herein relate to a frequency multiplier and a method therein. In particular, they relate to a power efficient frequency multiplier for generating an output signal with a specific frequency from an input signal.

BACKGROUND

Wireless communication devices usually comprise transceivers which comprising receivers and transmitters. A frequency multiplier, together with a low frequency oscillator, is able to provide high purity and stable signal sources for a transceiver in a wireless communication device. The frequency multiplier multiplies an input signal with a low frequency _η, to an output signal with a desired high frequency f_out. where f₀ut=n^* fin, and n is an integer multiplication factor. As the operation frequency of a wireless transceiver increases, e.g., at 71-76 GHz and 81 -86 GHz E-band or at 1 10-170 GHz D-band, the multiplication factor is probably large. For instance, a D-band signal source of 1 10 GHz to

170 GHz needs a frequency-multiplier-by-six, also called a frequency sixtupler, where n=6, or a frequency-multiplier-by-eight, where n=8.

There are many ways to obtain a frequency sixtupler by cascading a frequency tripler with a frequency doubler. For example, in KALLFASS, I. et al., A W-band Active Frequency- multiplier-by-six in Waveguide Package, German Microwave Conference, 2010, a frequency- multiplier-by-six is disclosed. In order to avoid a bandwidth limitation of λ/4 stubs at an output of a doubler, a balanced topology is described, where a single-ended input signal is transferred into differential outputs by an active balun. In ABBASI, M. et al., Single-Chip Frequency Multiplier Chains for Millimeter-Wave Signal Generation, IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, December 2009, vol. 57, no. 12, a sixtupler is disclosed which comprises a frequency tripler, a buffer amplifier, and a cascaded frequency doubler. The exiting frequency-multiplier-by-six has a problem of low power efficiency which is defined as:

n =Pout/(P_Dc+Pin) (1 ) where P_out denotes the output signal power at a frequency of 6^* _η and Ρ,_η denotes the input signal power at frequency _η, PDC denotes Direct Current (DC) power consumption. The power efficiency of the existing frequency sixtupler is less than or equal to 1 %. Adding a power amplifier can boost the sixtulper's output power and conversion gain, but cannot improve the power efficiency.

On the other hand, the power efficiency decreases usually as an order of the multiplier increases. For example, a frequency-multiplier-by-eight, n=8, has lower power efficiency than a frequency sixtupler, n=6. In other words, it becomes more challenge to increase the power efficiency for a frequency-multiplier-by-eight.

SUMMARY

Therefor it is an object of embodiments herein to provide a frequency multiplier with improved performance.

According to a first aspect of embodiments herein, the object is achieved by a frequency multiplier for generating an output signal with a specific frequency from an input signal. The frequency multiplier comprises a first stage to receive the input signal and generate even-order harmonics of the input signal. The frequency multiplier further comprises a second stage to receive the generated even-order harmonics and generate signals with the specific frequency by multiplying, mixing and amplifying the received even- order harmonics; and the second stage further combines the generated signals with the specific frequency to generate the output signal with the specific frequency. The frequency multiplier further comprises a transformer coupled between the first stage and the second stage. The frequency multiplier may further comprise a high pass or band pass filter coupled to an output of the second stage to suppress signals with undesired frequencies.

According to a second aspect of embodiments herein, the object is achieved by corresponding embodiments of a method in a frequency multiplier for generating an output signal with a specific frequency from an input signal. The method comprises generating even-order harmonics of an input signal in a first stage of the frequency multiplier. The method further comprises receiving the generated even-order harmonics in a second stage of the frequency multiplier via a transformer comprised in the frequency multiplier. The method further comprises generating signals with the specific frequency in the second stage by multiplying, mixing and amplifying the received even-order harmonics. The method further comprises combining the generated signals with the specific frequency in the second stage to generate the output signal with the specific frequency. The method may further comprise selecting the output signal with the specific frequency by a high pass or band pass filter comprised in the frequency multiplier and suppressing signals with undesired frequencies.

Since the output signal with the specific frequency is generated from different mechanisms and combined at the second stage, the frequency multiplier herein achieves good conversion gain, high power efficiency and output power.

Thus, embodiments herein provide a frequency multiplier with improved performance on conversion gain, output power and power efficiency.

BRIEF DESCRIPTION OF THE DRAWINGS

Examples of embodiments herein are described in more detail with reference to attached drawings in which:

Figure 1 is a general view of a frequency multiplier according to embodiments herein.

Figure 2 is a schematic diagram illustrating a frequency multiplier according to

embodiments herein.

Figure 3 is a flowchart depicting a method in a frequency multiplier according to

embodiments herein.

Figure 4 is a diagram illustrating spectrum for an input signal to the second stage of a

frequency-multiplier-by-8 according to embodiments herein.

Figure 5 is a diagram showing spectrum for an output signal of a frequency-multiplier-by-8 according to embodiments herein.

Figure 6 is a diagram showing conversion gain and power efficiency versus input signal power for a frequency-multiplier-by-8 according to embodiments herein. Figure 7 is a diagram showing output signal powers of different order harmonics versus input signal power for a frequency-multiplier-by-8 according to embodiments herein.

Figure 8 is a diagram showing conversion gain and power efficiency versus output signal frequency for a frequency-multiplier-by-8 according to embodiments herein. Figure 9 is a diagram showing output signal powers of different order harmonics versus output signal frequency for a frequency-multiplier-by-8 according to embodiments herein.

Figure 10 is a diagram showing output signal powers of different order harmonics versus input signal power for a frequency-multiplier-by-6 according to embodiments herein.

Figure 1 1 is a diagram showing conversion gain and power efficiency versus input signal power for a frequency-multiplier-by-6 according to embodiments herein.

Figure 12 is a block diagram illustrating a wireless communication device in which

embodiments herein may be implemented.

DETAILED DESCRIPTION

According to some embodiments, a general view of a frequency multiplier 100 for generating an output signal with a specific frequency from an input signal is shown in Figure 1. The specific frequency is a desired frequency generated by the frequency multiplier 100. The frequency multiplier 100 comprises two cascaded stages, a first stage 101 and a second stage 102. The first stage 101 is an even-order harmonics generator, which produces a 2nd, a 4th, a 6th, and a 8th... order harmonics of the input signal. The second stage 102 is a nonlinear converter, which receives the generated even-order harmonics and generates signals with the specific frequency by multiplying, mixing and amplifying the received even-order harmonics. The second stage 102 further combines the generated signals with the specific frequency to generate the output signal with the specific frequency. Further, there is a transformer 103 coupled between the first and second stages 101 ,102. The transformer 103 is to connect the first and second stages 101 ,102, and also to transform impedance between the first stage 101 and the second stage 102. Then, the generated output signal with the specific frequency is selected by a high pass or band pass filter 104 and signals with undesired frequencies are suppressed.

According to some embodiments, the frequency multiplier 100 which in these embodiments are referred to as a frequency multiplier 200, may be implemented by circuits shown in Figure 2, where the first stage 101 may be implemented by a circuit referred to as a first stage 201 , the second stage 102 may be implemented by a circuit referred to as a second stage 202, the transformer 103 may be implemented by a circuit referred to as a transformer 203, and the high pass or band pass filter 104 may be implemented by a circuit referred to as a high pass or band pass filter 204. As shown in Figure 2, the first stage 201 comprises a capacitive cross coupled transistor pair Q-|/Q-| . Although transistor Qi is shown as a Bipolar transistor having a base, a collector and an emitter, other type of transistor, such as Field-effect transistor having a gate, a drain and a source may be used. The first stage 201 also comprises coupled degeneration inductors L-|/ l_i at the emitters or sources of the transistor pair Q-|/Qi . Two inductors at the emitters are coupled with a mutual inductance, M-| . The coupled inductors are able to transfer a sing-ended input signal into differential signal outputs to drive two transistors Q1/Q1. Therefore, no balun is needed for the first stage 201 . As shown in Figure 2, the collectors or drains of the transistor pair Q-|/Q-|are connected together. As the first stage 101 in Figure 1 , the first stage 201 in Figure 2 is an even-order harmonics generator, where the generated 2nd and other high even-order harmonics are signals which will be used in the second stage 202. The second stage 202 comprises two transistors, a common-base or common-gate configured transistor <¾ and a common-emitter or common-source configured transistor (¾. The collectors or drains of the first and second transistors are connected together, and an emitter or source of the first transistor <¾ is coupled to a base or gate of the second transistor Q3 via a capacitor C2. Although transistor <¾ and Q3 are shown as Bipolar transistors, other type of transistors, such as Field-effect transistors may be used.

Between the first stage 201 and the second stage 202, there is the transformer 203.

The transformer 203 comprises a primary winding, i.e. inductor l_2, and a secondary winding, i.e. inductor L3, coupled with a mutual inductance, M2. The collectors or drains of the two transistors Q1 Q1 in the first stage 201 are connected together to the primary winding l_2 of the transformer 203. A DC supply for the transistors Q-|/Qi is connected with another terminal of L₂. The emitter or source of the first transistor <¾ and the base or gate of the second transistor Q3 via the capacitor C2 in the second stage 202 are connected to the secondary winding L3 of the transformer 203, and therefore are connected to the ground through the secondary winding L3 of the transformer 203.

The input signal to the second stage 202 is at the emitter or source of the (¾ and the base or gate of the Q3. The emitter or source of the Q3 is DC grounded via the secondary winding L₃. The base or gate of the <¾ is AC grounded by connecting to a voltage supplier V_b1 . As the frequency multiplier 100, the frequency multiplier 200 further comprises a high pass or band pass filter 204, connected between an output of the second stage 202 and an output of the frequency multiplier 200. The output signal of the frequency multiplier 200 is taken from the collectors or drains of the transistors <¾ and <¾ at the second stage 202 via a capacitor Co and the high pass or band pass filter 204. The high pass or band pass filter 204 is used to suppress signals with undesired frequencies at the output of the frequency multiplier 200.

According to some embodiments herein, the frequency multiplier 100, 200 may be a frequency-multiplier-by-six and the specific frequency of the output signal is 6 times of a frequency of the input signal. The second stage 102, 202 may be configured to receive the generated even-order harmonicas, such as the 2nd, 4th and 6th order harmonics. The second stage 102, 202 is configured to multiply the received 2nd order harmonic to a first signal with the frequency of 6 times the input signal frequency. The second stage 102, 202 is configured to mix the received 2nd and 4th order harmonics to a second signal with the frequency of 6 times the input signal frequency. The second stage 102, 202 is configured to amplify the received 6th order harmonic to a third signal with the frequency of 6 times the input signal frequency. The second stage 102, 202 is further configured to combine the first, the second and the third signals to generate the output signal with the specific frequency. The frequency-multiplier-by-six also uses a high pass or band pass filter to suppress signals with undesired frequencies.

According to some embodiments herein, the frequency multiplier 100, 200 may be a frequency-multiplier-by-8. In these embodiments, the specific frequency of the output signal is 8 times of a frequency of the input signal. The second stage 102, 202 is configured to receive the generated even-order harmonics, such as the 2nd, the 4th, the 6th and the 8th order harmonics. The second stage 102, 202 is configured to multiply the received 2nd and/or 4th order harmonics to a first signal with the frequency of 8 times the input signal frequency. The second stage 102, 202 is configured to mix the received 2nd and 6th order harmonics to a second signal with the frequency of 8 times the input signal frequency. The second stage 102, 202 is configured to amplify the received 8th harmonic to a third signal with the frequency of 8 times the input signal frequency. And further the second stage 102, 202 is configured to combine the first, the second and the third signals to generate the output signal with the specific frequency. The frequency-multiplier-by-eight also uses a high pass or band pass filter to suppress signals with undesired frequencies. Corresponding embodiments of a method in the frequency multiplier 100, 200 for generating an output signal with a specific frequency from an input signal will now be described with reference to Figure 3. As mentioned above, the frequency multiplier 100, 200 comprises the first stage 101 , 201 , the second stage 102, 202, the transformer 103, 203 and the high pass or band pass filter 104, 204. The method comprises the following actions.

Action 301

The first stage 101 , 201 of the frequency multiplier 100, 200 receives an input signal and generates even-order harmonics of the input signal.

Action 302

The second stage 102, 202 of the frequency multiplier 100, 200 receives the generated even-order harmonics via the transformer 103, 203.

Action 303

The second stage 102, 202 of the frequency multiplier 100, 200 generates signals with the specific frequency by multiplying, mixing and amplifying the received even-order harmonics.

Action 304

The second stage 102, 202 of the frequency multiplier 100, 200 combines the generated signals to generate the output signal with the specific frequency.

Action 305

The high pass or band pass filter 104, 204 of the frequency multiplier 100, 200 selects the output signal with the specific frequency and supresses signals with undesired frequencies.

In some embodiments wherein the frequency multiplier 100, 200 is a frequency- multiplier-by-six, then the specific frequency of the output signal is 6 times of a frequency of the input signal, the received harmonics by the second stage 102, 202 comprises at least the 2nd, the 4th and the 6th order harmonics. In these embodiments, Action 303 performed by the second stage 102, 202 of the frequency multiplier 100, 200 comprises multiplying the received 2nd harmonic to a first signal with the specific frequency; mixing the received 2nd and 4th harmonics to a second signal with the specific frequency; and amplifying the received 6th harmonic to a third signal with the specific frequency. In some embodiments wherein the frequency multiplier 100, 200 is a frequency- multiplier-by-8, then the specific frequency of the output signal is 8 times of a frequency of the input signal, the received harmonics by the second stage 102,102 comprises at least the 2nd, the 4th, the 6th and the 8th order harmonics. In these embodiments, Action 303 performed by the second stage 102, 202 of the frequency multiplier 100, 200 comprises multiplying the received 2nd order harmonic by 4 and/or 4th order harmonic by 2 to a first signal with the specific frequency; mixing the received 2nd and 6th harmonics to a second signal with the specific frequency; and amplifying the received 8th harmonic to a third signal with the specific frequency.

In order to show unique features and advantages of the frequency multiplier 100, 200 according embodiments herein, architectures and functions of the first stage 101 , 201 , the second stage 102, 202 and the transformer 103, 203 will be discussed in more detail in combination with some simulation results.

The first stage 101 , 201 is an even-order harmonics generator. In order to avoid using a balun to transfer a single-ended input into differential outputs, a differential low noise amplifier may be modified to be an even-order harmonic generator. The differential outputs of the low noise amplifier may be combined. As shown in Figure 2, the collectors or drains of the transistor pair are connected together so that the differential outputs are combined. Thus, the odd-order harmonics are suppressed due to phase cancellation, and the even-order harmonics are added in phase.

The even-order harmonic generator is put at the first stage so that the output power of the first stage 101 , 201 can be lower than that of the second stage 102, 202, to get good power efficiency. Two transistors in the transistor pair operate in class-C configuration, in a harmonic-rich manner, which consumes very little DC power. As a result, the power consumption of the first stage 101 , 201 is low, for example, when biased at a low base voltage of 0.63V, the DC current consumption of two transistors is 3 mA only at 1.5V DC supply voltage, and the power consumption is only 4.5 mW.

The second stage 102, 202 is a nonlinear converter. The even-order harmonics generated at the first stage 101 , 201 are fed into the second stage 202 via the transformer 103, 203. The even-order harmonics, 2nd, the 4th, the 6th, the 8th, etc. are converted into either the 6th order harmonic for the frequency-multiplier-by-6 or the 8th order harmonic for the frequency-multiplier-by-8 in the second stage 102, 202.

As discussed above, in the second stage 102, 202, there are two transistors (¾ and Q3. A simple nonlinear model is used to analyze the function of the second stage 102, 202. The nonlinear relationship between the base-emitter voltage, v_be(t), and the collector current i_c(t) is utilized to generate the output signal with the desired frequency, which can be represented by a polynomial

i_c(t) = α_!ΐ7( _6β + ₂v(t) _e + ₃v(t)l_e + ₄v(t)t_e + (1 )

For simplicity, it is assumed that two transistors, <¾ and <¾, have the same

nonlinearity, but their base-emitter voltages have 180 phase difference, due to different configurations. Combing the collector current from the two transistors yields

ictotai i = 2a₂v(t)L + 2a₄i⁷(t)¾_e + ···, (2)

Where only the even-order terms are remained and their coefficients are doubled, the odd-order terms are cancelled. Usually, the second-order term has major contribution to the nonlinear frequency conversion, thus, the conversion efficiency of the nonlinear converter, i.e. the second stage 202, is doubled comparing with a nonlinear converter with a single transistor.

As the first stage 101 , 102 is an even-order harmonics generator, which generates harmonic signals with voltages v₂f, v_4i, v_bi the base-emitter AC voltage of the first transistor <¾ in the second stage 102, 202 can be written as

t¾e( = v_2f + v_4f + v_6f + - -, (3)

Where, v_2nf = Acos(4nf ^■ n + φ) and n=1 , 2, 3, ... denotes the even-order harmonics generated by the first stage 101 , 201 . Due to the amplitudes of the harmonics decreases with increasing order, the high order harmonics, higher than 6, i.e. n>3 are not included in the Eq. (3).

Inserting Eq. (3) into Eq. (2), obtains

ic_to_tai i ^¾ 2a₂

+ vl_f + v _f + 2v_2fv_4f + 2v_2fv_6f + 2v_4fv_6f] + + v%_f + vt_f + lvl_fvl_f + lvl_fvl_f + vl_fvl_f +^■■■] (4)

For a frequency-multiplier-by-8, the 8th order harmonic is desired output, which is able to be obtained in the following terms on the right side of Eq. (4):

i_c,8th = 2 ₂v_4f + 2 ₄v_2f + 4- ₂v_2fv_6f (5)

The first and the second terms represent multiplication of the 4th order harmonic by 2 and the 2nd order harmonic by 4; while the third term represents mixing of the 2nd order and the 6th order harmonics.

Eq. (5) shows clearly that the second stage 102, 202 functions not only as a mixer, but also as a frequency multiplier. This is the reason that the second stage 102, 202 is called as a nonlinear converter, instead of a mixer or a multiplier. Due to the transistors' nonlinearity in the second stage102, 202 as discussed above, the different order harmonics will be mixed, multiplied and amplified to generate a signal at the desired or specific frequency. The signals with the specific frequency originated or generated from different mechanisms in the second stage 102, 202 are added inherently by the two transistors at the second stage 102, 202. Consequently, high conversion gain and power efficiency are obtained.

The transformer 103, 203 is connected between the first stage 101 , 201 and the second stage 102, 202. The transformer 103, 203 comprises two inductors coupled with the mutual inductance, M2. The transformer 103, 203 has multi-functions, such as provides impedance matching between the two stages; provides DC passes for transistors Qi and <¾; as a collector load for transistors Q1/Q1 ; as a reactive component to prevent the emitter of (¾ and the base of Q3 to be AC grounded. Simulations have been performed for a frequency-mulitiplier-by-8 according

embodiments herein. For a given input sinusoid signal at a frequency of _η=18.75 GHz with a power of 5 dBm, the spectrum of the input signal for the second stage 202, i.e. at point A in Figure 2, is shown in Figure 4. It can be seen that there are the 2nd, the 4th, and the 6th, etc. order harmonics and their amplitudes drop with increasing order.

Table 1 shows simulation results for the output signal power at different cases for a frequency-multiplier-by-8, where "Y" indicates that the particular harmonic presents at the input of the second stage 202, "N" indicates that the particular harmonic does not present at the input of the second stage 202. If the 6th and 8th order harmonics are removed by filters, the 2nd and the 4th order harmonics are dominant at the input of the second stage 202. The output signal power of the obtained 8th order harmonic, i.e. 8 _η=18.75*8=150 GHz, due to multiplication, 2 _ηχ4+4 _ηχ2, is -4.07 dBm, i.e. 0.39 mW, as listed in the 2nd row in Table 1. If the 6th and the 8th order harmonics are kept at the input of the second stage, the output signal power of the 8th order harmonic becomes 3.77 dBm, i.e. 2.38 mW, as listed in the 4th row in Table 1 . Thus, the multiplication contributes about 16.4% of the output signal power.

The simulation results also show that the 8th order harmonic at the input point A of the second stage 202 has a very small contribution to the output signal power, because the output signal power increases slightly, only 0.05 dBm, as the 8th order harmonic at the input point A is presented, i.e. 3.77 dBm instead of 3.72 dBm, as listed in the 4th row in Table 1 . Table 1 Simulated output signal power at different cases

The output signal spectrum of the frequency-multiplier-by-8 is shown in Figure 5, where the signal power for the 8^th order harmonic is 3.77 dBm which is dominant as the signal power for other order harmonics are below -10 dBm.

The simulation can also give details of DC power consumptions for each transistor in the first and second stages 201 , 202. Table 2 shows the simulation results, where the amplitude and phase of the 8th order harmonic contained in the collector currents generated by the common-base transistor <¾ and common-emitter transistor <¾ are also listed. The total DC power consumption for the frequency-multiplier-by-8 is 31 .2 mW.

Table 2 DC power consumption and amplitude/phase for the 8th order harmonic

As shown in Table 2, the 8th order harmonics generated by (¾ and Q3 have similar amplitudes and their phases difference is small, i.e. they are almost in-phase. Thus, the output signal power for the second stage 202 with two transistors according to embodiments herein, is almost doubled comparing to a nonlinear converter with a single transistor.

On the other hand, the DC power consumption of the second stage 202 with two transistors according to embodiments herein is almost twice as that for a single transistor nonlinear converter. However, the DC power consumption for the whole frequency multiplier 200 increases less than twice, since the DC power consumption of the first stage 201 is unchanged. Consequently, the power efficiency of the frequency multiplier according to embodiments herein is better than a frequency multiplier using a single transistor nonlinear converter. Figure 6 shows conversion gain and power efficiency versus input signal power, at frequency fj_n=18.75GHz, where x-axis represents input signal power, y-axis to the right represents power efficiency and y-axis to the left represents conversion gain. As the input frequency is 18.75 GHz, the output signal frequency for the frequency-mulitiplier-by-8 is 150 GHz. It can be seen that the frequency-multiplier-by-8 achieves a maximum conversion gain of -1.1 dB and a maximum power efficiency of 7.5%. This power efficiency is better than the existing frequency sixtupler and also better than a frequency sixtupler using a single transistor nonlinear converter.

Figure 7 shows output signal powers at different order harmonics versus input signal power. The frequency-multiplier-by-8 can deliver a maximum output power of 4.7 dBm which is about 4 dB larger than that of a frequency sixtupler using a single transistor nonlinear converter. The 8th order harmonic is about 14 dB larger than the undesired harmonics, as the input signal power is larger than 3 dBm. The performance of the frequency multiplier 100, 200 according to embodiments herein varies with the output signal frequency. Figure 8 shows conversion gain and power efficiency versus output signal frequency, where x-axis represents output signal frequency, y- axis to the right represents power efficiency and y-axis to the left represents conversion gain. In a frequency range from 144 GHz to 160 GHz, the conversion gain varies within -3.70 dBm to -1 .23 dBm, the power efficiency varies within 4.52% to 7.54%, when the input signal power is 5 dBm.

Figure 9 shows output signal power for different order harmonics as a function of output signal frequency. The output signal power of the 8th order harmonic varies between 0 dBm and 4 dBm in a frequency range from 144 GHz to 160 GHz. As the output signal frequency is larger than 153 GHz, the difference between the output signal powers for the 8th order harmonic and the 6th order harmonic is less than 10 dB.

Furthermore, although the frequency multiplier 100, 200 according to embodiments herein has been discussed and analysed as a frequency-multiplier-by-8, it is also applicable for implementing either a frequency quadrupler or a frequency sixtupler. When the frequency multiplier 100, 200 according to embodiments herein is implemented as a frequency sixtupler, e.g. an input signal frequency is 25 GHz and an output signal frequency is 150 GHz, the output signal power for different order harmonics versus the input signal power is shown in Figure 10. The maximum output signal power of the 6th order harmonic is 5.15 dBm. While the maximum output signal power for a sixtupler using a single transistor nonlinear converter is around 1 dBm only. The suppression of undesired harmonics is larger than 18 dB, as the input signal power is larger than 0.5 dBm.

Figure 11 shows conversion gain and power efficiency versus input signal power, where x-axis represents input signal power, y-axis to the right represents power efficiency and y-axis to the left represents conversion gain. The maximum power efficiency is 8.53%, when the input signal power is about 4.5 dBm. The corresponding conversion gain is -0.57 dB. This power efficiency is almost twice as much as that for a sixtupler using a single transistor nonlinear converter.

In summary, the frequency multiplier 100, 200 according embodiments herein has following unique features:

There is no filter or buffer amplifier between two stages, instead a transformer is connected between the two stages. The transformer also provides impedance

transformation.

The first stage is an even-order harmonics generator without utilizing balun.

The second stage has two transistors and their base-emitter voltages have 180 phase difference due to different configurations. Their collector currents are combined. The second stage has multi-function, for example, multiplying, mixing and amplifying the different order harmonics. The collectors or drains of the two transistors are connected together, and connected to the output of the frequency multiplier via a high-pass/band-pass filter.

These unique features of the frequency multiplier 100, 200 according to embodiments herein result in at least following advantages:

- High power efficiency, larger than 8% for the frequency-multiplier- by-6 and larger than 7% for the frequency-multiplier-by-8.

- Large output power, larger than 5 dBm for the frequency-multiplier- by-6 and larger than 4.6 dBm for the frequency-multiplier-by-8.

- The even-order harmonics generator without balun saves the chip area comparing with that of using a passive or an active balun, respectively. - All transistors in the frequency multiplier according to embodiments herein operate in class-B or C configuration with a low DC power consumption, while the output signal with a specific frequency is obtained via transistor's nonlinear converting.

The frequency multiplier 100, 200 according to embodiments herein is suitable for millimeter or macro wave transceivers as an RF signal source generator, for example to generate E-band or D-band signals, in a wireless communication device 1200 as shown in Figure 12. The wireless communication device 1200 comprises a Transceiver 1210, wherein the frequency multiplier 100, 200 may be implemented in. The wireless

communication device 1200 further comprises a Memory 1220 and a Processing unit 1230.

Those skilled in the art will understand that although transistors Qi , Q2, Q3 in the frequency multiplier 200 as shown in Figures 2 are Bipolar Junction Transistors (BJT), the frequency multiplier 200 may comprise any other types of transistors, such as Field-Effect Transistor (FET), Metal-Oxide-Semiconductor FET (MOSFET), Junction FET (JFET), etc. When using the word "comprise" or "comprising" it shall be interpreted as non- limiting, i.e. meaning "consist at least of".

The embodiments herein are not limited to the above described preferred

embodiments. Various alternatives, modifications and equivalents may be used. Therefore, the above embodiments should not be taken as limiting the scope of the invention, which is defined by the appending claims.

Claims

1 . A frequency multiplier (100; 200) for generating an output signal with a specific

frequency from an input signal, the frequency multiplier (100; 200) comprising:

a first stage (101 ; 201 ) to receive the input signal and generate even-order harmonics of the input signal;

a second stage (102; 202) to receive the generated even-order harmonics and generate signals with the specific frequency by multiplying, mixing and amplifying the received even-order harmonics; and wherein the second stage (102; 202) further combines the generated signals with the specific frequency to generate the output signal with the specific frequency;

a transformer (103; 203) coupled between the first stage and the second stage; and

a high pass or a band pass filter (104; 204), coupled to an output of the second stage (102; 202).

2. The frequency multiplier (100; 200) according to claim 1 , wherein the first stage (101 ;201 ) comprises two capacitive cross coupled transistors (Q-i ; Q-i ) with emitter or source degeneration inductors (l_i ; L-i ), collectors or drains of the two transistors are connected together to a primary winding (L2) of the transformer (203).

3. The frequency multiplier (100; 200) according to any of the claims 1-2, wherein the second stage (102; 202) comprises a first transistor (<¾) configured in common-base or common-gate configuration and a second transistor (Q3) configured in common- emitter or common-source configuration, wherein collectors or drains of the first and second transistors are connected together, and an emitter or source of the first transistor (<¾) is coupled to a base or gate of the second transistor(Q3) via a capacitor (C₂).

4. The frequency multiplier (100; 200) according to any of the claims 1-3, wherein the emitter or source of the first transistor (<¾) and the base or gate of the second transistor (Q3) via the capacitor (C2) are connected to a secondary winding (L3) of the transformer (203).

5. The frequency multiplier (100; 200) according to any of the claims 1-4, wherein the output signal with the specific frequency is outputted from the collectors or drains of the first and second transistors via a capacitor (Co) and the high pass or a band pass filter (104; 204).

6. The frequency multiplier (100; 200) according to any of the claims 1-5, wherein the frequency multiplier (100; 200) is a frequency-multiplier-by-six and the specific frequency of the output signal is 6 times of a frequency of the input signal, and wherein the generated even-order harmonics comprises at least a 2nd, a 4th and a 6th order harmonics, and wherein

the second stage (102; 202) is configured to receive the generated even-order harmonics and generate signals with the specific frequency by:

multiplying the received 2nd order harmonic to a first signal with the specific frequency;

mixing the received 2nd and 4th order harmonics to a second signal with the specific frequency; and

amplifying the received 6th order harmonic to a third signal with the specific frequency.

7. The frequency multiplier (100; 200) according to any of the claims 1-5, wherein the frequency multiplier (100; 200) is a frequency-multiplier-by-eight and the specific frequency of the output signal is 8 times of a frequency of the input signal, and wherein the generated even-order harmonics comprises at least 2nd, 4th, 6th and 8th order harmonics, and wherein

multiplying the received 2nd and/or 4th order harmonic to a first signal with the specific frequency;

mixing the received 2nd and 6th order harmonics to a second signal with the specific frequency; and

amplifying the received 8th order harmonic to a third signal with the specific frequency.

8. A microwave transceiver (1210) comprising a frequency multiplier (100; 200)

according to any of the claims 1 -7.

9. A wireless communication device (1200) comprising a frequency multiplier (100; 200) according to any of the claims 1 -7.

10. A method in a frequency multiplier (100; 200) for generating an output signal with a specific frequency from an input signal, the method comprising:

generating (301 ) even-order harmonics of an input signal in a first stage (101 ;

201 ) of the frequency multiplier (100; 200);

receiving (302) the generated even-order harmonics in a second stage (102; 202) of the frequency multiplier (100; 200) via a transformer (103; 203) comprised in the frequency multiplier (100; 200);

generating (303) signals with the specific frequency in the second stage (102;

202) by multiplying, mixing and amplifying the received even-order harmonics;

combining (304) the generated signals in the second stage (102; 202) to generate the output signal with the specific frequency; and

selecting (305) the output signal with the specific frequency by a high pass or band pass filter comprised in the frequency multiplier and suppressing signals with undesired frequencies.

1 1 . The method according to claim 10, wherein the specific frequency of the output signal is 6 times of a frequency of the input signal, and wherein the generated even-order harmonics comprises at least 2nd, 4th and 6th order harmonics, and wherein generating (303) signals with the specific frequency in the second stage (102; 202) by multiplying, mixing and amplifying the received even-order harmonics comprises: multiplying the received 2nd harmonic to a first signal with the specific frequency; mixing the received 2nd and 4th harmonics to a second signal with the specific frequency; and

amplifying the received 6th harmonic to a third signal with the specific frequency.

12. The method according to claim 10, wherein the specific frequency of the output signal is 8 times of a frequency of the input signal, and wherein the generated even-order harmonics comprises at least 2nd, 4th, 6th, and 8th order harmonics, and wherein generating (303) signals with the specific frequency in the second stage (102; 202) by multiplying, mixing and amplifying the received even-order harmonics comprises: multiplying the received 2nd and/or 4th harmonics to a first signal with the specific frequency; mixing the received 2nd and 6th harmonics to a second signal with the specific frequency; and

amplifying the received 8th harmonic to a third signal with the specific frequency.