JP2015530820A5 - - Google Patents

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Publication number
JP2015530820A5
JP2015530820A5 JP2015529866A JP2015529866A JP2015530820A5 JP 2015530820 A5 JP2015530820 A5 JP 2015530820A5 JP 2015529866 A JP2015529866 A JP 2015529866A JP 2015529866 A JP2015529866 A JP 2015529866A JP 2015530820 A5 JP2015530820 A5 JP 2015530820A5
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JP
Japan
Prior art keywords
digital code
signal
digital
programmable buffer
programmable
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JP2015529866A
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English (en)
Japanese (ja)
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JP5960362B2 (ja
JP2015530820A (ja
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Priority claimed from US13/598,513 external-priority patent/US9143121B2/en
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Publication of JP2015530820A publication Critical patent/JP2015530820A/ja
Publication of JP2015530820A5 publication Critical patent/JP2015530820A5/ja
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Publication of JP5960362B2 publication Critical patent/JP5960362B2/ja
Expired - Fee Related legal-status Critical Current
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JP2015529866A 2012-08-29 2013-08-21 クロック信号を調整するシステムおよび方法 Expired - Fee Related JP5960362B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/598,513 2012-08-29
US13/598,513 US9143121B2 (en) 2012-08-29 2012-08-29 System and method of adjusting a clock signal
PCT/US2013/056050 WO2014035771A2 (en) 2012-08-29 2013-08-21 System and method of adjusting a clock signal

Publications (3)

Publication Number Publication Date
JP2015530820A JP2015530820A (ja) 2015-10-15
JP2015530820A5 true JP2015530820A5 (enExample) 2015-12-03
JP5960362B2 JP5960362B2 (ja) 2016-08-02

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ID=49083804

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015529866A Expired - Fee Related JP5960362B2 (ja) 2012-08-29 2013-08-21 クロック信号を調整するシステムおよび方法

Country Status (5)

Country Link
US (1) US9143121B2 (enExample)
EP (1) EP2891245A2 (enExample)
JP (1) JP5960362B2 (enExample)
CN (1) CN104584431A (enExample)
WO (1) WO2014035771A2 (enExample)

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KR20240131776A (ko) * 2023-02-24 2024-09-02 삼성전자주식회사 플래시 메모리 및 그것의 읽기 리커버리 방법

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