JP5960362B2 - クロック信号を調整するシステムおよび方法 - Google Patents

クロック信号を調整するシステムおよび方法 Download PDF

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Publication number
JP5960362B2
JP5960362B2 JP2015529866A JP2015529866A JP5960362B2 JP 5960362 B2 JP5960362 B2 JP 5960362B2 JP 2015529866 A JP2015529866 A JP 2015529866A JP 2015529866 A JP2015529866 A JP 2015529866A JP 5960362 B2 JP5960362 B2 JP 5960362B2
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signal
programmable
digital code
digital
clock signal
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Japanese (ja)
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JP2015530820A5 (enExample
JP2015530820A (ja
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ゴンザレス、ジェイソン
ダング、バンナム
ジュ、ジー
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Qualcomm Inc
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Qualcomm Inc
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
    • H03K5/1565—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Manipulation Of Pulses (AREA)
JP2015529866A 2012-08-29 2013-08-21 クロック信号を調整するシステムおよび方法 Expired - Fee Related JP5960362B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/598,513 2012-08-29
US13/598,513 US9143121B2 (en) 2012-08-29 2012-08-29 System and method of adjusting a clock signal
PCT/US2013/056050 WO2014035771A2 (en) 2012-08-29 2013-08-21 System and method of adjusting a clock signal

Publications (3)

Publication Number Publication Date
JP2015530820A JP2015530820A (ja) 2015-10-15
JP2015530820A5 JP2015530820A5 (enExample) 2015-12-03
JP5960362B2 true JP5960362B2 (ja) 2016-08-02

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JP2015529866A Expired - Fee Related JP5960362B2 (ja) 2012-08-29 2013-08-21 クロック信号を調整するシステムおよび方法

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US (1) US9143121B2 (enExample)
EP (1) EP2891245A2 (enExample)
JP (1) JP5960362B2 (enExample)
CN (1) CN104584431A (enExample)
WO (1) WO2014035771A2 (enExample)

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US9263107B1 (en) * 2014-11-06 2016-02-16 Qualcomm Incorporated Load isolation for pad signal monitoring
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JP7071621B2 (ja) * 2018-01-22 2022-05-19 株式会社ソシオネクスト 送信回路及び集積回路
US10890938B2 (en) * 2018-08-20 2021-01-12 Taiwan Semiconductor Manufacturing Company Ltd. Clock duty cycle adjustment and calibration circuit and method of operating same
US11437992B2 (en) 2020-07-30 2022-09-06 Mobix Labs, Inc. Low-loss mm-wave CMOS resonant switch
CN112787633B (zh) * 2020-12-24 2023-02-03 海光信息技术股份有限公司 占空比校准电路、高速接口电路、处理器及电子设备
CN112636720B (zh) * 2020-12-24 2022-11-25 海光信息技术股份有限公司 输入输出信号的占空比校准电路、高速接口电路及处理器
CN113484565B (zh) * 2021-07-14 2024-02-13 国网新疆电力有限公司电力科学研究院 用于校准低频交流信号的直流信号生成装置及校准方法
US12375089B2 (en) 2022-06-30 2025-07-29 Microchip Technology Incorporated Reducing duty cycle mismatch of clock signals for clock tracking circuits
KR102722312B1 (ko) * 2022-12-12 2024-10-25 주식회사 퀄리타스반도체 클럭 듀티 캘리브레이션 장치 및 방법
KR20240131776A (ko) * 2023-02-24 2024-09-02 삼성전자주식회사 플래시 메모리 및 그것의 읽기 리커버리 방법

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JP2008160610A (ja) * 2006-12-26 2008-07-10 Nec Electronics Corp クロックデューティ変更回路
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Also Published As

Publication number Publication date
WO2014035771A2 (en) 2014-03-06
CN104584431A (zh) 2015-04-29
EP2891245A2 (en) 2015-07-08
WO2014035771A3 (en) 2014-07-03
US9143121B2 (en) 2015-09-22
JP2015530820A (ja) 2015-10-15
US20140062559A1 (en) 2014-03-06

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