BR112016024960A2 - circuitos de malha fechada por rede de baixo ruído - Google Patents

circuitos de malha fechada por rede de baixo ruído

Info

Publication number
BR112016024960A2
BR112016024960A2 BR112016024960A BR112016024960A BR112016024960A2 BR 112016024960 A2 BR112016024960 A2 BR 112016024960A2 BR 112016024960 A BR112016024960 A BR 112016024960A BR 112016024960 A BR112016024960 A BR 112016024960A BR 112016024960 A2 BR112016024960 A2 BR 112016024960A2
Authority
BR
Brazil
Prior art keywords
signal
closed loop
low noise
loop circuits
signals
Prior art date
Application number
BR112016024960A
Other languages
English (en)
Inventor
Savla Anup
Bicakci Ara
Yang Jeongsik
Wang Shen
Cat Nguyen Thinh
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112016024960A2 publication Critical patent/BR112016024960A2/pt

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/05—Compensating for non-linear characteristics of the controlled oscillator

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

aspectos dos circuitos e métodos para gerar um sinal oscilante são revelados. o circuito inclui um detector de fase configurado para emitir primeiro e segundo sinais em resposta a uma diferença de fase entre dois sinais de entrada. o detector de fase é ainda configurado para desativar o primeiro sinal ao emitir o segundo sinal e para desativar o segundo sinal ao emitir o primeiro sinal. o circuito inclui ainda um oscilador controlado por tensão (vco), configurado para gerar um sinal oscilante tendo uma frequência sintonizável em resposta ao primeiro e segundo sinais.
BR112016024960A 2014-04-30 2015-04-15 circuitos de malha fechada por rede de baixo ruído BR112016024960A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/266,730 US20150318860A1 (en) 2014-04-30 2014-04-30 Low noise phase locked loops
PCT/US2015/025967 WO2015167805A1 (en) 2014-04-30 2015-04-15 Low noise phase locked loops

Publications (1)

Publication Number Publication Date
BR112016024960A2 true BR112016024960A2 (pt) 2017-08-15

Family

ID=53177354

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112016024960A BR112016024960A2 (pt) 2014-04-30 2015-04-15 circuitos de malha fechada por rede de baixo ruído

Country Status (7)

Country Link
US (1) US20150318860A1 (pt)
EP (1) EP3138201A1 (pt)
JP (1) JP6679499B2 (pt)
KR (1) KR20160146752A (pt)
CN (1) CN106537784B (pt)
BR (1) BR112016024960A2 (pt)
WO (1) WO2015167805A1 (pt)

Families Citing this family (8)

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US9553715B2 (en) * 2014-12-22 2017-01-24 Opel Solar, Inc. Optical phase detector for an optical phase lock loop
US10120064B2 (en) * 2015-03-19 2018-11-06 Nxp Usa, Inc. Radar system and method with saturation detection and reset
TWI554037B (zh) * 2015-04-16 2016-10-11 群聯電子股份有限公司 時脈資料回復電路模組、記憶體儲存裝置及相位鎖定方法
CN110061737B (zh) * 2019-04-26 2023-05-16 海光信息技术股份有限公司 相位锁定检测输出电路及全数字锁相环系统
JP7301766B2 (ja) * 2020-03-04 2023-07-03 株式会社東芝 位相補正装置、測距装置及び位相変動検出装置
JP7301771B2 (ja) * 2020-03-19 2023-07-03 株式会社東芝 位相補正装置、測距装置及び位相変動検出装置
WO2022041277A1 (zh) * 2020-08-31 2022-03-03 华为技术有限公司 锁相环和射频收发机
TWI739640B (zh) * 2020-10-27 2021-09-11 瑞昱半導體股份有限公司 電路和相關晶片

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US5307028A (en) * 1992-10-16 1994-04-26 Ncr Corporation Phase-and-frequency mode/phase mode detector with the same gain in both modes
US5304952A (en) * 1993-05-10 1994-04-19 National Semiconductor Corporation Lock sensor circuit and method for phase lock loop circuits
JPH07142966A (ja) * 1993-11-12 1995-06-02 Sanyo Electric Co Ltd 逓倍回路
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JP4015793B2 (ja) * 2000-02-16 2007-11-28 株式会社東芝 位相比較回路およびｐｌｌ回路
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JP2004120443A (ja) * 2002-09-27 2004-04-15 Matsushita Electric Ind Co Ltd 遅延調整回路
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Also Published As

Publication number Publication date
JP2017518685A (ja) 2017-07-06
CN106537784A (zh) 2017-03-22
EP3138201A1 (en) 2017-03-08
US20150318860A1 (en) 2015-11-05
WO2015167805A1 (en) 2015-11-05
JP6679499B2 (ja) 2020-04-15
KR20160146752A (ko) 2016-12-21
CN106537784B (zh) 2019-08-02

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Legal Events

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B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

Free format text: REFERENTE A 5A ANUIDADE.

B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: REFERENTE AO DESPACHO 8.6 PUBLICADO NA RPI 2562 DE 2020-02-11

B350 Update of information on the portal [chapter 15.35 patent gazette]