MX2014011819A - Bucle de enganche de fase de velocidad de respuesta programable. - Google Patents

Bucle de enganche de fase de velocidad de respuesta programable.

Info

Publication number
MX2014011819A
MX2014011819A MX2014011819A MX2014011819A MX2014011819A MX 2014011819 A MX2014011819 A MX 2014011819A MX 2014011819 A MX2014011819 A MX 2014011819A MX 2014011819 A MX2014011819 A MX 2014011819A MX 2014011819 A MX2014011819 A MX 2014011819A
Authority
MX
Mexico
Prior art keywords
output
pll
slew rate
locked loop
signal
Prior art date
Application number
MX2014011819A
Other languages
English (en)
Other versions
MX342336B (es
Inventor
Justin Walraven
Original Assignee
Thomas & Betts Int Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomas & Betts Int Llc filed Critical Thomas & Betts Int Llc
Publication of MX2014011819A publication Critical patent/MX2014011819A/es
Publication of MX342336B publication Critical patent/MX342336B/es

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J9/00—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting
    • H02J9/04—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source
    • H02J9/06—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source with automatic change-over, e.g. UPS systems
    • H02J9/062—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source with automatic change-over, e.g. UPS systems for AC powered loads
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J9/00—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting
    • H02J9/04—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source
    • H02J9/06—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source with automatic change-over, e.g. UPS systems
    • H02J9/068—Electronic means for switching from one power supply to another power supply, e.g. to avoid parallel connection
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/14—Preventing false-lock or pseudo-lock of the PLL

Abstract

Un sistema incluye un primer circuito de bucle de enganche de fase (PLL), un limitador de velocidad de respuesta y un segundo PLL. El primer PLL se configura para recibir una señal de entrada, generar una primera salida que identifica una frecuencia asociada con la señal de entrada, y generar una segunda salida que identifica la información de la fase asociada con la señal de entrada. El limitador de la velocidad de respuesta se configura para recibir la primera salida del primer PLL, determinar si la frecuencia de la primera salida cambia a más de una tasa predeterminada, y generar una primera señal que indica si la frecuencia cambia a más de la tasa predeterminada. El segundo PLL se configura para recibir la primera señal del limitador de la velocidad de respuesta, recibir la segunda salida del primer PLL, y generar una señal de salida que identifica una información del ángulo o la fase en función de la primera señal y la segunda salida.
MX2014011819A 2013-10-08 2014-09-30 Bucle de enganche de fase de velocidad de respuesta programable. MX342336B (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201361888150P 2013-10-08 2013-10-08
US14/486,233 US9350362B2 (en) 2013-10-08 2014-09-15 Programmable slew rate phase locked loop

Publications (2)

Publication Number Publication Date
MX2014011819A true MX2014011819A (es) 2015-04-29
MX342336B MX342336B (es) 2016-09-26

Family

ID=51660342

Family Applications (1)

Application Number Title Priority Date Filing Date
MX2014011819A MX342336B (es) 2013-10-08 2014-09-30 Bucle de enganche de fase de velocidad de respuesta programable.

Country Status (4)

Country Link
US (1) US9350362B2 (es)
EP (1) EP2860873B1 (es)
ES (1) ES2590730T3 (es)
MX (1) MX342336B (es)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106787124B (zh) * 2015-11-20 2019-04-23 维谛技术有限公司 一种增强ups在油机旁路运行时锁相性能的方法
US10797513B1 (en) * 2019-04-08 2020-10-06 Abb Schweiz Ag Technologies for interactive predictive control of uninterruptible power supply systems
US10931287B1 (en) * 2019-08-22 2021-02-23 Micron Technology, Inc. Phase locked loop circuit

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5473533A (en) 1993-12-02 1995-12-05 Best Power Technology, Incorporated Method and apparatus for efficient phase and frequency coherence locking optimized for digital systems
US5606581A (en) 1994-03-17 1997-02-25 Myers; Glen A. Method and apparatus for the cancellation of interference in electrical systems
US6163687A (en) 1997-07-22 2000-12-19 Intel Corporation Tuning module for a dual frequency PLL synthesized tuner
EP1229653A1 (en) 2001-02-02 2002-08-07 Semiconductor Ideas to The Market (ItoM) BV Feedback loop with slew rate limiter
US7881413B2 (en) 2001-03-02 2011-02-01 Adc Telecommunications, Inc. Digital PLL with conditional holdover
US7224951B1 (en) 2003-09-11 2007-05-29 Xilinx, Inc. PMA RX in coarse loop for high speed sampling
US7376158B2 (en) 2004-04-22 2008-05-20 Scientific-Atlanta, Inc. Rate limited control mechanism for MPEG PCR dejittering
US7065734B2 (en) * 2004-06-02 2006-06-20 Lsi Logic Corporation Method of generating multiple hardware description language configurations for a phase locked loop from a single generic model for integrated circuit design
US20060001494A1 (en) 2004-07-02 2006-01-05 Bruno Garlepp Cascaded locked-loop circuits deriving high-frequency, low noise clock signals from a jittery, low-frequency reference
JP4655683B2 (ja) 2005-03-01 2011-03-23 日本電気株式会社 スルーレート調整回路およびスルーレート調整方法
EP1783913A1 (en) 2005-11-08 2007-05-09 Deutsche Thomson-Brandt Gmbh Switchable PLL circuit including two loops
US7602253B2 (en) 2006-12-11 2009-10-13 Silicon Image, Inc. Adaptive bandwidth phase locked loop with feedforward divider
US20080218278A1 (en) 2007-03-05 2008-09-11 Exar Corporation Means to control pll phase slew rate
US8093930B2 (en) 2008-03-19 2012-01-10 Integrated Device Technology, Inc High frequency fractional-N divider
GB2475514A (en) 2009-11-20 2011-05-25 Aeroflex Internat Ltd Phase locked loop with coarse tuning circuit operated by a cycle slip detector
US8154329B2 (en) 2009-12-31 2012-04-10 Motorola Solutions, Inc. Device and method for phase compensation
US20140062605A1 (en) * 2012-08-31 2014-03-06 Motorola Solutions, Inc. Method and apparatus for a synthesizer architecture

Also Published As

Publication number Publication date
EP2860873A1 (en) 2015-04-15
US20150097602A1 (en) 2015-04-09
EP2860873B1 (en) 2016-06-15
MX342336B (es) 2016-09-26
US9350362B2 (en) 2016-05-24
ES2590730T3 (es) 2016-11-23

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