JP2017157214A5 - - Google Patents

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JP2017157214A5
JP2017157214A5 JP2017033466A JP2017033466A JP2017157214A5 JP 2017157214 A5 JP2017157214 A5 JP 2017157214A5 JP 2017033466 A JP2017033466 A JP 2017033466A JP 2017033466 A JP2017033466 A JP 2017033466A JP 2017157214 A5 JP2017157214 A5 JP 2017157214A5
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memory array
interface
host device
memory
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JP2017157214A (ja
JP7022511B2 (ja
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JP2017033466A 2016-03-03 2017-02-24 インモジュール機能を遂行するメモリモジュール Active JP7022511B2 (ja)

Applications Claiming Priority (12)

Application Number Priority Date Filing Date Title
US201662303347P 2016-03-03 2016-03-03
US201662303343P 2016-03-03 2016-03-03
US201662303352P 2016-03-03 2016-03-03
US201662303349P 2016-03-03 2016-03-03
US62/303,352 2016-03-03
US62/303,347 2016-03-03
US62/303,343 2016-03-03
US62/303,349 2016-03-03
US201662347569P 2016-06-08 2016-06-08
US62/347,569 2016-06-08
US15/213,386 2016-07-18
US15/213,386 US10592114B2 (en) 2016-03-03 2016-07-18 Coordinated in-module RAS features for synchronous DDR compatible memory

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JP2017157214A JP2017157214A (ja) 2017-09-07
JP2017157214A5 true JP2017157214A5 (enExample) 2020-03-05
JP7022511B2 JP7022511B2 (ja) 2022-02-18

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JP2017033466A Active JP7022511B2 (ja) 2016-03-03 2017-02-24 インモジュール機能を遂行するメモリモジュール

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US (4) US10592114B2 (enExample)
JP (1) JP7022511B2 (enExample)
KR (1) KR102712052B1 (enExample)
CN (1) CN107153616B (enExample)
TW (2) TWI756767B (enExample)

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