JP2017152572A - 半導体装置およびヒューズ切断方法 - Google Patents
半導体装置およびヒューズ切断方法 Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
- H01L23/5258—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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Abstract
Description
また、特許文献2においては、積層したヒューズ素子をコンタクトで接続し、コンタクト部をレーザーによって切断することで、切断不良が発生し難い方法が提示されている。
従来方法の他の例である特許文献2においては、ヒューズ素子が積層に配置され、さらに上層のヒューズ素子にくびれを持たせることで、特許文献1で起こる短絡の危険性が低減されている。しかし、本構造では下層部のヒューズ素子にもレーザーが少なからず照射される構成となっている。この下層部のヒューズ素子に着目すると、ヒューズ素子上の膜は厚く、さらにレーザーから受けるエネルギーは不十分な状態の為、ヒューズ素子が完全に気化しない、もしくは再付着する危険性が非常に高い状態となる。そのことにより、上層部のヒューズ素子と下層部のヒューズ素子がヒューズ再付着により短絡する可能性が出てきてしまう。
図1は、本発明における第1の実施形態にかかる半導体装置の平面図である。上部ヒューズ素子11および下部ヒューズ配線12が配置され、上部ヒューズ素子11のレーザー照射領域42の中心には上部ヒューズ素子11と下部ヒューズ配線12とを接続するためのヒューズ接続コンタクト13が配置されている。上部ヒューズ素子11と下部ヒューズ配線12とヒューズ接続コンタクト13とが1つのヒューズ素子を構成している。上部ヒューズ素子11はレーザーの照射を受けるレーザー照射領域42とレーザー照射領域42から延びている上部ヒューズ配線部14を有している。図1は複数のヒューズ素子が並列に配置された状態を示しており、これら複数のヒューズ素子の上は、保護膜開口領域43が設けられている。保護膜開口領域43は、半導体装置の上部に配置される例えばシリコン窒化膜のような最終保護膜が除去された領域となっている。
下部配線がシリコン窒化膜23により保護されている為、図3に示すように下部配線のレイアウトは自由に行うことが可能となり、レイアウト設計が容易となる。下部ヒューズ配線12は保護膜開口領域43の一辺から他の一辺に渡りその下方に屈曲して配置されていても良い。下部ヒューズ配線12同士を接続したり、複数の下部ヒューズ配線12に分岐したりすることも可能である。
12 下部ヒューズ配線
13 ヒューズ接続コンタクト
14 上部ヒューズ配線部
15 ヒューズ素子
16 ヒューズ切断痕
17 ヒューズ切れ残り
18 ヒューズ再付着
21 第1の層間絶縁膜
22 第3の層間絶縁膜
23 シリコン窒化膜
24 第4の層間絶縁膜
25 第2の層間絶縁膜
26 最終保護膜
30 ヒューズ間絶縁膜
31 シリコン基板
41 レーザースポット
42 レーザー照射領域
43 保護膜開口領域
Claims (9)
- 半導体基板と、
前記半導体基板の表面に設けられた第1の層間絶縁膜と、
前記第1の層間絶縁膜の上に設けられた下部ヒューズ配線と、
前記下部ヒューズ配線の上に設けられたヒューズ間絶縁膜と、
前記ヒューズ間絶縁膜の上に設けられた、レーザー照射領域および上部ヒューズ配線部を有する上部ヒューズ素子と、
前記ヒューズ間絶縁膜に設けられた、前記下部ヒューズ配線と前記上部ヒューズ素子とを接続するヒューズ接続コンタクトと、
前記ヒューズ間絶縁膜の上に設けられた第2の層間絶縁膜と、からなり、
前記レーザー照射領域は円形であり、前記ヒューズ接続コンタクトは前記レーザー照射領域の中心に配置されていることを特徴とする半導体装置。 - 前記第2の層間絶縁膜は、第3の酸化膜と、シリコン窒化膜と、第4の酸化膜とからなることを特徴とする請求項1記載の半導体装置。
- 前記上部ヒューズ素子の上部ヒューズ配線部が隣り合う上部ヒューズ素子の上部ヒューズ配線部と隣接しないことを特徴とする請求項1または2に記載の半導体装置。
- 前記レーザー照射領域は、平面視的に円形であることを特徴とする請求項1乃至3のいずれか1項記載の半導体装置。
- 前記第2の層間絶縁膜の上に設けられた最終保護膜と、
前記最終保護膜の、前記レーザー照射領域を含む前記上部ヒューズ領域の上方となる領域に設けられた保護膜開口領域と、をさらに有し、
前記下部ヒューズ配線は、前記保護膜開口領域の一辺から他の一辺に渡り、その下方に屈曲して配置されていることを特徴とする請求項1乃至4のいずれか1項に記載の半導体装置。 - 前記下部ヒューズ配線と前記上部ヒューズ素子が異なる材料からなることを特徴とする請求項1乃至5のいずれか1項記載の半導体装置。
- 前記上部ヒューズ素子と前記ヒューズ接続コンタクトが異なる材料からなることを特徴とする請求項1乃至請求項6のいずれか1項記載の半導体装置。
- 前記上部ヒューズ配線部は、前記下部ヒューズ配線よりも幅が小さいことを特徴とする請求項1乃至7のいずれか1項記載の半導体装置。
- 請求項1乃至8のいずれかの1項に記載の半導体装置において、前記レーザー照射領域にレーザービームを照射して、前記レーザー照射領域を溶融気化させることで切断することを特徴とするヒューズ切断方法。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
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JP2016034493A JP6636823B2 (ja) | 2016-02-25 | 2016-02-25 | 半導体装置およびヒューズ切断方法 |
TW106105522A TWI695476B (zh) | 2016-02-25 | 2017-02-20 | 半導體裝置以及熔絲的切斷方法 |
US15/437,822 US10043749B2 (en) | 2016-02-25 | 2017-02-21 | Semiconductor device |
KR1020170023503A KR20170100432A (ko) | 2016-02-25 | 2017-02-22 | 반도체 장치 및 퓨즈의 절단 방법 |
CN201710103120.8A CN107123635B (zh) | 2016-02-25 | 2017-02-24 | 半导体装置及熔丝的切断方法 |
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JP2016034493A JP6636823B2 (ja) | 2016-02-25 | 2016-02-25 | 半導体装置およびヒューズ切断方法 |
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JP6636823B2 JP6636823B2 (ja) | 2020-01-29 |
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JP (1) | JP6636823B2 (ja) |
KR (1) | KR20170100432A (ja) |
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JP6777243B2 (ja) * | 2017-10-19 | 2020-10-28 | 富士電機株式会社 | 半導体装置及び半導体装置の製造方法 |
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JP3625560B2 (ja) * | 1995-05-16 | 2005-03-02 | 株式会社東芝 | 半導体装置およびヒューズの切断方法 |
JP2000269342A (ja) * | 1999-03-12 | 2000-09-29 | Toshiba Microelectronics Corp | 半導体集積回路および半導体集積回路の製造方法 |
US6225652B1 (en) * | 1999-08-02 | 2001-05-01 | Clear Logic, Inc. | Vertical laser fuse structure allowing increased packing density |
KR100335498B1 (ko) * | 1999-12-22 | 2002-05-08 | 윤종용 | 반도체 소자의 퓨즈부 구조 및 그 형성방법 |
US6295721B1 (en) * | 1999-12-28 | 2001-10-02 | Taiwan Semiconductor Manufacturing Company | Metal fuse in copper dual damascene |
KR100425452B1 (ko) * | 2001-07-04 | 2004-03-30 | 삼성전자주식회사 | 반도체 소자의 리페어 퓨즈 개구 방법 |
KR100455378B1 (ko) * | 2002-02-09 | 2004-11-06 | 삼성전자주식회사 | 반도체 소자의 퓨즈 오픈방법 |
KR100463047B1 (ko) * | 2002-03-11 | 2004-12-23 | 삼성전자주식회사 | 반도체 장치의 퓨즈 박스 및 그 제조방법 |
KR100476694B1 (ko) * | 2002-11-07 | 2005-03-17 | 삼성전자주식회사 | 반도체 장치의 퓨즈 구조물 및 그 제조 방법 |
JP4964472B2 (ja) * | 2006-01-31 | 2012-06-27 | 半導体特許株式会社 | 半導体装置 |
KR100722774B1 (ko) * | 2006-05-09 | 2007-05-30 | 삼성전자주식회사 | 반도체 장치의 퓨즈 구조물 및 그 제조 방법 |
US8969999B2 (en) * | 2011-10-27 | 2015-03-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin-like field effect transistor (FinFET) based, metal-semiconductor alloy fuse device and method of manufacturing same |
US9679845B2 (en) * | 2014-05-08 | 2017-06-13 | Intel Corporation | Necked interconnect fuse structure for integrated circuits |
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- 2017-02-21 US US15/437,822 patent/US10043749B2/en not_active Expired - Fee Related
- 2017-02-22 KR KR1020170023503A patent/KR20170100432A/ko unknown
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TW201743426A (zh) | 2017-12-16 |
KR20170100432A (ko) | 2017-09-04 |
US10043749B2 (en) | 2018-08-07 |
US20170250136A1 (en) | 2017-08-31 |
TWI695476B (zh) | 2020-06-01 |
CN107123635A (zh) | 2017-09-01 |
CN107123635B (zh) | 2021-07-23 |
JP6636823B2 (ja) | 2020-01-29 |
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