JP2017126630A - 炭化珪素半導体装置の製造方法 - Google Patents
炭化珪素半導体装置の製造方法 Download PDFInfo
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- JP2017126630A JP2017126630A JP2016004222A JP2016004222A JP2017126630A JP 2017126630 A JP2017126630 A JP 2017126630A JP 2016004222 A JP2016004222 A JP 2016004222A JP 2016004222 A JP2016004222 A JP 2016004222A JP 2017126630 A JP2017126630 A JP 2017126630A
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Abstract
【解決手段】トレンチ5の形成後、基体おもて面を覆う部分13aの厚さt1がトレンチ5の内壁5aを覆う部分13bの厚さt2よりも厚くなるように、基体おもて面およびトレンチの内壁5aに堆積膜13を成膜する。そして、トレンチ5の内壁5aが露出するまで堆積膜13の全体の厚さを薄くし、基体おもて面を覆う部分13aのみ堆積膜13を残す。この状態で犠牲酸化を行うことで、基体おもて面と堆積膜13との界面に犠牲酸化による熱酸化膜がほぼ成長しないため、n+型ソース領域4の厚さがほぼ維持される。一方、トレンチ5の内壁5aのダメージ層は、犠牲酸化により酸化されて熱酸化膜となり除去される。このため、その後、この熱酸化膜を除去することでダメージ層の除去された略平坦な内壁を有するトレンチ5が得られる。
【選択図】図4
Description
実施の形態にかかる半導体装置の製造方法について、耐圧1200Vクラスのトレンチゲート型MOSFETを作製(製造)する場合を例に説明する。図1〜8は、実施の形態にかかる半導体装置の製造途中の状態を示す断面図である。まず、図1に示すように、炭化珪素(SiC)からなるn+型ドレイン層となるn+型出発基板(以下、n+型炭化珪素基板とする)1のおもて面に、n-型ドリフト層2となるn-型炭化珪素エピタキシャル層を成長させる。以下、n+型炭化珪素基板1上にn-型炭化珪素エピタキシャル層を成長させてなる炭化珪素エピタキシャル基板を炭化珪素基体(半導体ウエハ(半導体基板))とする。
2 n-型ドリフト層
3 p型ベース領域
4 n+型ソース領域
5 トレンチ
5a ダメージ層が形成された状態のトレンチの内壁
5b ダメージ層が除去された状態のトレンチの内壁
6 ゲート絶縁膜
7 ゲート電極
8 層間絶縁膜
9 ソース電極
10 ドレイン電極
11 酸化膜
13 堆積膜
13a 堆積膜の、基体おもて面を覆う部分
13b 堆積膜の、トレンチの内壁を覆う部分
14 熱酸化膜
t1 堆積膜の、基体おもて面を覆う部分の厚さ
t1’ 薄膜化後の堆積膜の、基体おもて面を覆う部分の厚さ
t2 堆積膜の、トレンチの内壁を覆う部分の厚さ
t3 熱酸化膜の厚さ
Claims (5)
- 炭化珪素からなる半導体基板にトレンチを有する炭化珪素半導体装置の製造方法であって、
前記半導体基板に前記トレンチを形成する第1工程と、
前記半導体基板の表面および前記トレンチの内壁に、前記トレンチの内壁での厚さよりも前記半導体基板の表面での厚さが厚くなるように堆積膜を形成する第2工程と、
前記堆積膜の、前記トレンチの内壁を覆う部分を除去し、前記トレンチの内壁を露出させる第3工程と、
前記第3工程の後、犠牲酸化により前記トレンチの内壁に酸化膜を成長させる第4工程と、
前記堆積膜および前記酸化膜を除去する第5工程と、
を含むことを特徴とする炭化珪素半導体装置の製造方法。 - 前記第3工程では、前記堆積膜の厚さを均一に薄くして前記トレンチの内壁を露出させることを特徴とする請求項1に記載の炭化珪素半導体装置の製造方法。
- 前記第2工程では、前記堆積膜として酸化シリコン膜、窒化シリコン膜またはシリコン膜を形成することを特徴とする請求項1または2に記載の炭化珪素半導体装置の製造方法。
- 前記第1工程の前に、前記半導体基板の、前記トレンチを形成する側の主面に所定の素子構造を形成する工程をさらに含むことを特徴とする請求項1〜3のいずれか一つに記載の炭化珪素半導体装置の製造方法。
- 前記第1工程の前に、
第1導電型の前記半導体基板の、前記トレンチを形成する側の主面に、第2導電型の第1半導体領域を形成する工程と、
前記第1半導体領域の内部に、第1導電型の第2半導体領域を選択的に形成する工程と、をさらに含み、
前記第1工程では、前記第2半導体領域および前記第1半導体領域を深さ方向に貫通する前記トレンチを形成し、
前記第5工程の後、前記トレンチの内部にゲート絶縁膜を介してゲート電極を形成することを特徴とする請求項4に記載の炭化珪素半導体装置の製造方法。
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