JP2016514372A - 金属酸化物半導体ｔｆｔ用誘電体膜のピンホール評価方法 - Google Patents

金属酸化物半導体ｔｆｔ用誘電体膜のピンホール評価方法 Download PDF

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Publication number
JP2016514372A
JP2016514372A JP2016500719A JP2016500719A JP2016514372A JP 2016514372 A JP2016514372 A JP 2016514372A JP 2016500719 A JP2016500719 A JP 2016500719A JP 2016500719 A JP2016500719 A JP 2016500719A JP 2016514372 A JP2016514372 A JP 2016514372A
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Japan
Prior art keywords
active layer
dielectric layer
layer
thickness
etchant
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JP2016500719A
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English (en)
Japanese (ja)
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JP2016514372A5 (enExample
Inventor
ドンキル イム
ドンキル イム
タエ キュング ウォン
タエ キュング ウォン
セオンミー チョウ
セオンミー チョウ
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Applied Materials Inc
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Applied Materials Inc
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Publication of JP2016514372A publication Critical patent/JP2016514372A/ja
Publication of JP2016514372A5 publication Critical patent/JP2016514372A5/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/20—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by the properties tested or measured, e.g. structural or electrical properties
    • H10P74/203—Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/23—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes
    • H10P74/235—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes comprising optical enhancement of defects or not-directly-visible states

Landscapes

  • Thin Film Transistor (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2016500719A 2013-03-12 2014-03-06 金属酸化物半導体ｔｆｔ用誘電体膜のピンホール評価方法 Pending JP2016514372A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201361778223P 2013-03-12 2013-03-12
US61/778,223 2013-03-12
PCT/US2014/021086 WO2014158955A1 (en) 2013-03-12 2014-03-06 Pinhole evaluation method of dielectric films for metal oxide semiconductor tft

Publications (2)

Publication Number Publication Date
JP2016514372A true JP2016514372A (ja) 2016-05-19
JP2016514372A5 JP2016514372A5 (enExample) 2016-09-23

Family

ID=51528892

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016500719A Pending JP2016514372A (ja) 2013-03-12 2014-03-06 金属酸化物半導体ｔｆｔ用誘電体膜のピンホール評価方法

Country Status (6)

Country Link
US (1) US9245809B2 (enExample)
JP (1) JP2016514372A (enExample)
KR (1) KR101757400B1 (enExample)
CN (1) CN105009297B (enExample)
TW (1) TWI567997B (enExample)
WO (1) WO2014158955A1 (enExample)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019125743A (ja) * 2018-01-18 2019-07-25 トヨタ自動車株式会社 半導体装置の製造方法
JP2024027384A (ja) * 2022-08-17 2024-03-01 住友電気工業株式会社 受光素子の製造方法
WO2025258264A1 (ja) * 2024-06-10 2025-12-18 株式会社ジャパンディスプレイ 積層構造体、薄膜トランジスタ、および電子機器

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111599707A (zh) * 2020-05-27 2020-08-28 广州粤芯半导体技术有限公司 钝化层微裂纹的检测方法

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JPS56152247A (en) * 1980-04-26 1981-11-25 Mitsubishi Electric Corp Testing method for semiconductor device
JPS63115331A (ja) * 1986-11-04 1988-05-19 Matsushita Electronics Corp ピンホールの検査方法
JPH05226367A (ja) * 1992-02-14 1993-09-03 Fuji Xerox Co Ltd 半導体素子の製造方法
JPH0677484A (ja) * 1992-08-27 1994-03-18 Sharp Corp 薄膜トランジスタ及びその製造方法
JPH07283282A (ja) * 1994-04-08 1995-10-27 Sony Corp 絶縁膜の欠陥検出方法
JPH0831898A (ja) * 1994-07-18 1996-02-02 Hitachi Ltd 半導体ウエハの酸化膜評価方法
JPH1022283A (ja) * 1996-07-05 1998-01-23 Nippon Steel Corp 半導体装置の製造方法
JP2807679B2 (ja) * 1988-07-08 1998-10-08 住友シチックス株式会社 シリコン基板の絶縁膜欠陥検出方法
JP2005268507A (ja) * 2004-03-18 2005-09-29 Furukawa Electric Co Ltd:The 電界効果トランジスタ及びその製造方法
JP2008141113A (ja) * 2006-12-05 2008-06-19 Canon Inc エッチング方法、パターン形成方法、薄膜トランジスタの製造方法及びエッチング液

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JPS60140729A (ja) * 1983-12-28 1985-07-25 Oki Electric Ind Co Ltd 半導体素子膜の欠陥検査方法
EP0608628A3 (en) * 1992-12-25 1995-01-18 Kawasaki Steel Co Method for manufacturing a semiconductor device with a multilayer connection structure.
JP3685678B2 (ja) * 2000-03-21 2005-08-24 沖電気工業株式会社 半導体ウエハの評価方法
US6440870B1 (en) * 2000-07-12 2002-08-27 Applied Materials, Inc. Method of etching tungsten or tungsten nitride electrode gates in semiconductor structures
JP2004221379A (ja) * 2003-01-16 2004-08-05 Matsushita Electric Ind Co Ltd 絶縁膜の評価方法
US7524744B2 (en) * 2003-02-19 2009-04-28 Shin-Etsu Handotai Co., Ltd. Method of producing SOI wafer and SOI wafer
US20050029226A1 (en) * 2003-08-07 2005-02-10 Advanced Power Technology, Inc. Plasma etching using dibromomethane addition
US6949481B1 (en) 2003-12-09 2005-09-27 Fasl, Llc Process for fabrication of spacer layer with reduced hydrogen content in semiconductor device
US20090001360A1 (en) * 2007-06-29 2009-01-01 Masaya Nakayama Organic el display and method for producing the same
JP5330739B2 (ja) * 2007-06-29 2013-10-30 ユー・ディー・シー アイルランド リミテッド 有機ｅｌ表示装置およびその製造方法
KR101412761B1 (ko) 2008-01-18 2014-07-02 삼성디스플레이 주식회사 박막 트랜지스터 기판 및 이의 제조 방법
US8258511B2 (en) 2008-07-02 2012-09-04 Applied Materials, Inc. Thin film transistors using multiple active channel layers
CN102110625B (zh) * 2009-12-24 2012-07-25 中芯国际集成电路制造(上海)有限公司 一种针孔类生长缺陷的检测方法
CN103098185B (zh) 2010-08-20 2017-02-08 应用材料公司 形成无氢含硅介电薄膜的方法
WO2012092020A2 (en) 2010-12-30 2012-07-05 Applied Materials, Inc. Thin film deposition using microwave plasma

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56152247A (en) * 1980-04-26 1981-11-25 Mitsubishi Electric Corp Testing method for semiconductor device
JPS63115331A (ja) * 1986-11-04 1988-05-19 Matsushita Electronics Corp ピンホールの検査方法
JP2807679B2 (ja) * 1988-07-08 1998-10-08 住友シチックス株式会社 シリコン基板の絶縁膜欠陥検出方法
JPH05226367A (ja) * 1992-02-14 1993-09-03 Fuji Xerox Co Ltd 半導体素子の製造方法
JPH0677484A (ja) * 1992-08-27 1994-03-18 Sharp Corp 薄膜トランジスタ及びその製造方法
JPH07283282A (ja) * 1994-04-08 1995-10-27 Sony Corp 絶縁膜の欠陥検出方法
JPH0831898A (ja) * 1994-07-18 1996-02-02 Hitachi Ltd 半導体ウエハの酸化膜評価方法
JPH1022283A (ja) * 1996-07-05 1998-01-23 Nippon Steel Corp 半導体装置の製造方法
JP2005268507A (ja) * 2004-03-18 2005-09-29 Furukawa Electric Co Ltd:The 電界効果トランジスタ及びその製造方法
JP2008141113A (ja) * 2006-12-05 2008-06-19 Canon Inc エッチング方法、パターン形成方法、薄膜トランジスタの製造方法及びエッチング液

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019125743A (ja) * 2018-01-18 2019-07-25 トヨタ自動車株式会社 半導体装置の製造方法
JP7052367B2 (ja) 2018-01-18 2022-04-12 株式会社デンソー 半導体装置の製造方法
JP2024027384A (ja) * 2022-08-17 2024-03-01 住友電気工業株式会社 受光素子の製造方法
WO2025258264A1 (ja) * 2024-06-10 2025-12-18 株式会社ジャパンディスプレイ 積層構造体、薄膜トランジスタ、および電子機器

Also Published As

Publication number Publication date
US9245809B2 (en) 2016-01-26
KR20150127144A (ko) 2015-11-16
CN105009297B (zh) 2019-06-14
TWI567997B (zh) 2017-01-21
CN105009297A (zh) 2015-10-28
KR101757400B1 (ko) 2017-07-12
TW201507166A (zh) 2015-02-16
WO2014158955A1 (en) 2014-10-02
US20140273312A1 (en) 2014-09-18

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