JP2016505859A5 - - Google Patents

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Publication number
JP2016505859A5
JP2016505859A5 JP2015555297A JP2015555297A JP2016505859A5 JP 2016505859 A5 JP2016505859 A5 JP 2016505859A5 JP 2015555297 A JP2015555297 A JP 2015555297A JP 2015555297 A JP2015555297 A JP 2015555297A JP 2016505859 A5 JP2016505859 A5 JP 2016505859A5
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JP
Japan
Prior art keywords
scan
output
ports
input
test
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Application number
JP2015555297A
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English (en)
Japanese (ja)
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JP2016505859A (ja
JP6444317B2 (ja
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Priority claimed from US13/749,623 external-priority patent/US8839063B2/en
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Publication of JP2016505859A5 publication Critical patent/JP2016505859A5/ja
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Publication of JP6444317B2 publication Critical patent/JP6444317B2/ja
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JP2015555297A 2013-01-24 2014-01-24 スキャンテストリソースの動的アロケーションのための回路及び方法 Active JP6444317B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/749,623 2013-01-24
US13/749,623 US8839063B2 (en) 2013-01-24 2013-01-24 Circuits and methods for dynamic allocation of scan test resources
PCT/US2014/012891 WO2014116914A1 (en) 2013-01-24 2014-01-24 Circuits and methods for dynamic allocation of scan test resources

Publications (3)

Publication Number Publication Date
JP2016505859A JP2016505859A (ja) 2016-02-25
JP2016505859A5 true JP2016505859A5 (enExample) 2017-03-02
JP6444317B2 JP6444317B2 (ja) 2018-12-26

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JP2015555297A Active JP6444317B2 (ja) 2013-01-24 2014-01-24 スキャンテストリソースの動的アロケーションのための回路及び方法

Country Status (4)

Country Link
US (1) US8839063B2 (enExample)
JP (1) JP6444317B2 (enExample)
CN (1) CN104903736B (enExample)
WO (1) WO2014116914A1 (enExample)

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* Cited by examiner, † Cited by third party
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US9689922B2 (en) * 2013-12-20 2017-06-27 Advantest Corporation Online design validation for electronic devices
TWI629493B (zh) * 2014-10-29 2018-07-11 南韓商因諾帝歐股份有限公司 積體電路晶片測試裝置，方法及系統
US10217498B2 (en) * 2016-09-12 2019-02-26 Qualcomm Incorporated Techniques for preventing tampering with PROM settings
CN110687437A (zh) * 2019-09-03 2020-01-14 天津大学 一种扫描测试压缩的优化方法
US11105853B1 (en) 2020-02-28 2021-08-31 International Business Machines Corporation Empirical LBIST latch switching and state probability determination
US11733290B2 (en) * 2020-03-31 2023-08-22 Advantest Corporation Flexible sideband support systems and methods

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US5195050A (en) * 1990-08-20 1993-03-16 Eastman Kodak Company Single chip, mode switchable, matrix multiplier and convolver suitable for color image processing
FI100136B (fi) * 1993-10-01 1997-09-30 Nokia Telecommunications Oy Menetelmä integroidun piirin testaamiseksi sekä integroitu piiri
US5383143A (en) * 1994-03-30 1995-01-17 Motorola, Inc. Self re-seeding linear feedback shift register (LFSR) data processing system for generating a pseudo-random test bit stream and method of operation
US5732246A (en) * 1995-06-07 1998-03-24 International Business Machines Corporation Programmable array interconnect latch
EP0758771B1 (en) * 1995-08-10 1998-06-03 Hewlett-Packard GmbH An electronic circuit or board tester and a method of testing an electronic device
US5867507A (en) * 1995-12-12 1999-02-02 International Business Machines Corporation Testable programmable gate array and associated LSSD/deterministic test methodology
WO1997029384A1 (en) * 1996-02-06 1997-08-14 Telefonaktiebolaget Lm Ericsson (Publ) Assembly and method for testing integrated circuit devices
US5991909A (en) * 1996-10-15 1999-11-23 Mentor Graphics Corporation Parallel decompressor and related methods and apparatuses
US5991898A (en) * 1997-03-10 1999-11-23 Mentor Graphics Corporation Arithmetic built-in self test of multiple scan-based integrated circuits
JP2000353783A (ja) * 1999-04-05 2000-12-19 Matsushita Electric Ind Co Ltd 半導体装置
US6327687B1 (en) * 1999-11-23 2001-12-04 Janusz Rajski Test pattern compression for an integrated circuit test environment
US7028239B2 (en) 2000-12-29 2006-04-11 Intel Corporation Microprocessor on-chip testing architecture and implementation
US6950974B1 (en) * 2001-09-07 2005-09-27 Synopsys Inc. Efficient compression and application of deterministic patterns in a logic BIST architecture
JP2004037254A (ja) * 2002-07-03 2004-02-05 Matsushita Electric Ind Co Ltd スキャンテスト装置
JP2004191149A (ja) * 2002-12-10 2004-07-08 Matsushita Electric Ind Co Ltd スキャンテスト回路およびテスト方法
JP2006329876A (ja) * 2005-05-27 2006-12-07 Nec Electronics Corp 半導体集積回路及びそのテスト方法
US7487419B2 (en) 2005-06-15 2009-02-03 Nilanjan Mukherjee Reduced-pin-count-testing architectures for applying test patterns
JP2007003423A (ja) * 2005-06-24 2007-01-11 Toshiba Corp 半導体集積回路およびその制御方法
DE602006015084D1 (de) * 2005-11-02 2010-08-05 Nxp Bv Ic-testverfahren und vorrichtungen
CN1996035B (zh) * 2005-12-31 2012-01-25 旺玖科技股份有限公司 用于多芯片组件的具有可规划扫描链的装置
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US8566658B2 (en) * 2011-03-25 2013-10-22 Lsi Corporation Low-power and area-efficient scan cell for integrated circuit testing

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