JP6444317B2 - スキャンテストリソースの動的アロケーションのための回路及び方法 - Google Patents

スキャンテストリソースの動的アロケーションのための回路及び方法 Download PDF

Info

Publication number
JP6444317B2
JP6444317B2 JP2015555297A JP2015555297A JP6444317B2 JP 6444317 B2 JP6444317 B2 JP 6444317B2 JP 2015555297 A JP2015555297 A JP 2015555297A JP 2015555297 A JP2015555297 A JP 2015555297A JP 6444317 B2 JP6444317 B2 JP 6444317B2
Authority
JP
Japan
Prior art keywords
scan
ports
output
input
test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2015555297A
Other languages
English (en)
Japanese (ja)
Other versions
JP2016505859A5 (enExample
JP2016505859A (ja
Inventor
アジット パレクジ ルビン
アジット パレクジ ルビン
スリヴァス　ラヴィ
ラヴィ スリヴァス
ナラヤナン プラカシュ
ナラヤナン プラカシュ
シェティ ミラン
シェティ ミラン
Original Assignee
日本テキサス・インスツルメンツ株式会社
テキサス インスツルメンツ インコーポレイテッド
テキサス インスツルメンツ インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本テキサス・インスツルメンツ株式会社, テキサス インスツルメンツ インコーポレイテッド, テキサス インスツルメンツ インコーポレイテッド filed Critical 日本テキサス・インスツルメンツ株式会社
Publication of JP2016505859A publication Critical patent/JP2016505859A/ja
Publication of JP2016505859A5 publication Critical patent/JP2016505859A5/ja
Application granted granted Critical
Publication of JP6444317B2 publication Critical patent/JP6444317B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318572—Input/Output interfaces

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP2015555297A 2013-01-24 2014-01-24 スキャンテストリソースの動的アロケーションのための回路及び方法 Active JP6444317B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/749,623 US8839063B2 (en) 2013-01-24 2013-01-24 Circuits and methods for dynamic allocation of scan test resources
US13/749,623 2013-01-24
PCT/US2014/012891 WO2014116914A1 (en) 2013-01-24 2014-01-24 Circuits and methods for dynamic allocation of scan test resources

Publications (3)

Publication Number Publication Date
JP2016505859A JP2016505859A (ja) 2016-02-25
JP2016505859A5 JP2016505859A5 (enExample) 2017-03-02
JP6444317B2 true JP6444317B2 (ja) 2018-12-26

Family

ID=51208740

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015555297A Active JP6444317B2 (ja) 2013-01-24 2014-01-24 スキャンテストリソースの動的アロケーションのための回路及び方法

Country Status (4)

Country Link
US (1) US8839063B2 (enExample)
JP (1) JP6444317B2 (enExample)
CN (1) CN104903736B (enExample)
WO (1) WO2014116914A1 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9689922B2 (en) * 2013-12-20 2017-06-27 Advantest Corporation Online design validation for electronic devices
TWI629493B (zh) * 2014-10-29 2018-07-11 南韓商因諾帝歐股份有限公司 積體電路晶片測試裝置，方法及系統
US10217498B2 (en) * 2016-09-12 2019-02-26 Qualcomm Incorporated Techniques for preventing tampering with PROM settings
CN110687437A (zh) * 2019-09-03 2020-01-14 天津大学 一种扫描测试压缩的优化方法
US11105853B1 (en) 2020-02-28 2021-08-31 International Business Machines Corporation Empirical LBIST latch switching and state probability determination
US11733290B2 (en) * 2020-03-31 2023-08-22 Advantest Corporation Flexible sideband support systems and methods

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5195050A (en) * 1990-08-20 1993-03-16 Eastman Kodak Company Single chip, mode switchable, matrix multiplier and convolver suitable for color image processing
FI100136B (fi) * 1993-10-01 1997-09-30 Nokia Telecommunications Oy Menetelmä integroidun piirin testaamiseksi sekä integroitu piiri
US5383143A (en) * 1994-03-30 1995-01-17 Motorola, Inc. Self re-seeding linear feedback shift register (LFSR) data processing system for generating a pseudo-random test bit stream and method of operation
US5732246A (en) * 1995-06-07 1998-03-24 International Business Machines Corporation Programmable array interconnect latch
DE69502827T2 (de) * 1995-08-10 1998-10-15 Hewlett Packard Gmbh Elektronischer Schaltungs- oder Kartenprüfer und Verfahren zur Prüfung einer elektronischen Vorrichtung
US5867507A (en) * 1995-12-12 1999-02-02 International Business Machines Corporation Testable programmable gate array and associated LSSD/deterministic test methodology
DE69739438D1 (de) * 1996-02-06 2009-07-16 Ericsson Telefon Ab L M Anordnung und verfahren zur prüfung von integrierten schaltungseinrichtungen
US5991909A (en) * 1996-10-15 1999-11-23 Mentor Graphics Corporation Parallel decompressor and related methods and apparatuses
US5991898A (en) * 1997-03-10 1999-11-23 Mentor Graphics Corporation Arithmetic built-in self test of multiple scan-based integrated circuits
JP2000353783A (ja) * 1999-04-05 2000-12-19 Matsushita Electric Ind Co Ltd 半導体装置
US6327687B1 (en) * 1999-11-23 2001-12-04 Janusz Rajski Test pattern compression for an integrated circuit test environment
US7028239B2 (en) 2000-12-29 2006-04-11 Intel Corporation Microprocessor on-chip testing architecture and implementation
US6950974B1 (en) * 2001-09-07 2005-09-27 Synopsys Inc. Efficient compression and application of deterministic patterns in a logic BIST architecture
JP2004037254A (ja) * 2002-07-03 2004-02-05 Matsushita Electric Ind Co Ltd スキャンテスト装置
JP2004191149A (ja) * 2002-12-10 2004-07-08 Matsushita Electric Ind Co Ltd スキャンテスト回路およびテスト方法
JP2006329876A (ja) * 2005-05-27 2006-12-07 Nec Electronics Corp 半導体集積回路及びそのテスト方法
US7487419B2 (en) 2005-06-15 2009-02-03 Nilanjan Mukherjee Reduced-pin-count-testing architectures for applying test patterns
JP2007003423A (ja) * 2005-06-24 2007-01-11 Toshiba Corp 半導体集積回路およびその制御方法
EP1946131B1 (en) * 2005-11-02 2010-06-23 Nxp B.V. Ic testing methods and apparatus
CN1996035B (zh) * 2005-12-31 2012-01-25 旺玖科技股份有限公司 用于多芯片组件的具有可规划扫描链的装置
US8522096B2 (en) 2010-11-02 2013-08-27 Syntest Technologies, Inc. Method and apparatus for testing 3D integrated circuits
US8566658B2 (en) * 2011-03-25 2013-10-22 Lsi Corporation Low-power and area-efficient scan cell for integrated circuit testing

Also Published As

Publication number Publication date
CN104903736B (zh) 2019-03-15
US8839063B2 (en) 2014-09-16
US20140208177A1 (en) 2014-07-24
WO2014116914A1 (en) 2014-07-31
CN104903736A (zh) 2015-09-09
JP2016505859A (ja) 2016-02-25

Similar Documents

Publication Publication Date Title
JP5537158B2 (ja) 低消費電力スキャンテスト技術および装置
JP6444317B2 (ja) スキャンテストリソースの動的アロケーションのための回路及び方法
US8650524B1 (en) Method and apparatus for low-pin count testing of integrated circuits
US8904256B1 (en) Method and apparatus for low-pin count testing of integrated circuits
US11073556B2 (en) Low pin count reversible scan architecture
US8671320B2 (en) Integrated circuit comprising scan test circuitry with controllable number of capture pulses
US11815555B2 (en) Universal compactor architecture for testing circuits
US8819508B2 (en) Scan test circuitry configured to prevent violation of multiplexer select signal constraints during scan testing
US9335377B2 (en) Test-per-clock based on dynamically-partitioned reconfigurable scan chains
US20160349318A1 (en) Dynamic Clock Chain Bypass
US11150299B2 (en) Flexible isometric decompressor architecture for test compression
US20110175638A1 (en) Semiconductor integrated circuit and core test circuit
JP6654456B2 (ja) テストポイント回路、シーケンシャルテスト用スキャンフリップフロップ、半導体装置及び設計装置
US20090063921A1 (en) Staggered LBIST Clock Sequence for Noise (di/dt) Amelioration
US11747399B2 (en) Scan test control decoder with storage elements for use within integrated circuit (IC) devices having limited test interface
US10288682B2 (en) Integrated electronic device having a test architecture, and test method thereof
CN102156259A (zh) 一种集成电路的测试方法及一种集成电路
US6650136B2 (en) Method and apparatus to enhance testability of logic coupled to IO buffers
US12306246B2 (en) Partial chain reconfiguration for test time reduction
US20170140838A1 (en) Scan compression architecture for highly compressed designs and associated methods

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20150724

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20170123

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20170123

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20180131

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20180427

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20180629

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20180731

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20181114

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20181127

R150 Certificate of patent or registration of utility model

Ref document number: 6444317

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313117

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R360 Written notification for declining of transfer of rights

Free format text: JAPANESE INTERMEDIATE CODE: R360

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250