CN104903736B - 用于动态分配扫描测试资源的电路和方法 - Google Patents

用于动态分配扫描测试资源的电路和方法 Download PDF

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Publication number
CN104903736B
CN104903736B CN201480003921.1A CN201480003921A CN104903736B CN 104903736 B CN104903736 B CN 104903736B CN 201480003921 A CN201480003921 A CN 201480003921A CN 104903736 B CN104903736 B CN 104903736B
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China
Prior art keywords
scanning
output
dut
input
port
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Chinese (zh)
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CN104903736A (zh
Inventor
R·A·帕瑞克基
S·拉维
P·纳拉亚南
M·谢蒂
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Texas Instruments Inc
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Texas Instruments Inc
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318572—Input/Output interfaces

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
CN201480003921.1A 2013-01-24 2014-01-24 用于动态分配扫描测试资源的电路和方法 Active CN104903736B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/749,623 US8839063B2 (en) 2013-01-24 2013-01-24 Circuits and methods for dynamic allocation of scan test resources
US13/749,623 2013-01-24
PCT/US2014/012891 WO2014116914A1 (en) 2013-01-24 2014-01-24 Circuits and methods for dynamic allocation of scan test resources

Publications (2)

Publication Number Publication Date
CN104903736A CN104903736A (zh) 2015-09-09
CN104903736B true CN104903736B (zh) 2019-03-15

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN201480003921.1A Active CN104903736B (zh) 2013-01-24 2014-01-24 用于动态分配扫描测试资源的电路和方法

Country Status (4)

Country Link
US (1) US8839063B2 (enExample)
JP (1) JP6444317B2 (enExample)
CN (1) CN104903736B (enExample)
WO (1) WO2014116914A1 (enExample)

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US9689922B2 (en) * 2013-12-20 2017-06-27 Advantest Corporation Online design validation for electronic devices
TWI629493B (zh) * 2014-10-29 2018-07-11 南韓商因諾帝歐股份有限公司 積體電路晶片測試裝置，方法及系統
US10217498B2 (en) * 2016-09-12 2019-02-26 Qualcomm Incorporated Techniques for preventing tampering with PROM settings
CN110687437A (zh) * 2019-09-03 2020-01-14 天津大学 一种扫描测试压缩的优化方法
US11105853B1 (en) 2020-02-28 2021-08-31 International Business Machines Corporation Empirical LBIST latch switching and state probability determination
US11733290B2 (en) * 2020-03-31 2023-08-22 Advantest Corporation Flexible sideband support systems and methods

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US5195050A (en) * 1990-08-20 1993-03-16 Eastman Kodak Company Single chip, mode switchable, matrix multiplier and convolver suitable for color image processing
FI100136B (fi) * 1993-10-01 1997-09-30 Nokia Telecommunications Oy Menetelmä integroidun piirin testaamiseksi sekä integroitu piiri
US5383143A (en) * 1994-03-30 1995-01-17 Motorola, Inc. Self re-seeding linear feedback shift register (LFSR) data processing system for generating a pseudo-random test bit stream and method of operation
US5732246A (en) * 1995-06-07 1998-03-24 International Business Machines Corporation Programmable array interconnect latch
EP0758771B1 (en) * 1995-08-10 1998-06-03 Hewlett-Packard GmbH An electronic circuit or board tester and a method of testing an electronic device
US5867507A (en) * 1995-12-12 1999-02-02 International Business Machines Corporation Testable programmable gate array and associated LSSD/deterministic test methodology
CN1084878C (zh) * 1996-02-06 2002-05-15 艾利森电话股份有限公司 测试集成电路器件的设备和方法
US5991909A (en) * 1996-10-15 1999-11-23 Mentor Graphics Corporation Parallel decompressor and related methods and apparatuses
US5991898A (en) * 1997-03-10 1999-11-23 Mentor Graphics Corporation Arithmetic built-in self test of multiple scan-based integrated circuits
JP2000353783A (ja) * 1999-04-05 2000-12-19 Matsushita Electric Ind Co Ltd 半導体装置
US6327687B1 (en) * 1999-11-23 2001-12-04 Janusz Rajski Test pattern compression for an integrated circuit test environment
US7028239B2 (en) 2000-12-29 2006-04-11 Intel Corporation Microprocessor on-chip testing architecture and implementation
US6950974B1 (en) * 2001-09-07 2005-09-27 Synopsys Inc. Efficient compression and application of deterministic patterns in a logic BIST architecture
JP2004037254A (ja) * 2002-07-03 2004-02-05 Matsushita Electric Ind Co Ltd スキャンテスト装置
JP2004191149A (ja) * 2002-12-10 2004-07-08 Matsushita Electric Ind Co Ltd スキャンテスト回路およびテスト方法
JP2006329876A (ja) * 2005-05-27 2006-12-07 Nec Electronics Corp 半導体集積回路及びそのテスト方法
US7487419B2 (en) 2005-06-15 2009-02-03 Nilanjan Mukherjee Reduced-pin-count-testing architectures for applying test patterns
JP2007003423A (ja) * 2005-06-24 2007-01-11 Toshiba Corp 半導体集積回路およびその制御方法
WO2007069097A1 (en) * 2005-11-02 2007-06-21 Nxp B.V. Ic testing methods and apparatus
CN1996035B (zh) * 2005-12-31 2012-01-25 旺玖科技股份有限公司 用于多芯片组件的具有可规划扫描链的装置
US8522096B2 (en) 2010-11-02 2013-08-27 Syntest Technologies, Inc. Method and apparatus for testing 3D integrated circuits
US8566658B2 (en) * 2011-03-25 2013-10-22 Lsi Corporation Low-power and area-efficient scan cell for integrated circuit testing

Also Published As

Publication number Publication date
US8839063B2 (en) 2014-09-16
WO2014116914A1 (en) 2014-07-31
JP6444317B2 (ja) 2018-12-26
JP2016505859A (ja) 2016-02-25
US20140208177A1 (en) 2014-07-24
CN104903736A (zh) 2015-09-09

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