JP2016501477A5 - - Google Patents

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Publication number
JP2016501477A5
JP2016501477A5 JP2015542828A JP2015542828A JP2016501477A5 JP 2016501477 A5 JP2016501477 A5 JP 2016501477A5 JP 2015542828 A JP2015542828 A JP 2015542828A JP 2015542828 A JP2015542828 A JP 2015542828A JP 2016501477 A5 JP2016501477 A5 JP 2016501477A5
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JP
Japan
Prior art keywords
transistor
electrically connected
source
analog
drain
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JP2015542828A
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English (en)
Japanese (ja)
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JP2016501477A (ja
JP6529435B2 (ja
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Priority claimed from US13/677,858 external-priority patent/US8975948B2/en
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JP2015542828A 2012-11-15 2013-11-15 ワイドコモンモードレンジ送信ゲート Active JP6529435B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/677,858 US8975948B2 (en) 2012-11-15 2012-11-15 Wide common mode range transmission gate
US13/677,858 2012-11-15
PCT/US2013/070339 WO2014078677A1 (en) 2012-11-15 2013-11-15 Wide common mode range transmission gate

Publications (3)

Publication Number Publication Date
JP2016501477A JP2016501477A (ja) 2016-01-18
JP2016501477A5 true JP2016501477A5 (enExample) 2017-01-05
JP6529435B2 JP6529435B2 (ja) 2019-06-12

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ID=50681139

Family Applications (1)

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JP2015542828A Active JP6529435B2 (ja) 2012-11-15 2013-11-15 ワイドコモンモードレンジ送信ゲート

Country Status (4)

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US (1) US8975948B2 (enExample)
JP (1) JP6529435B2 (enExample)
CN (1) CN104769844B (enExample)
WO (1) WO2014078677A1 (enExample)

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US9362962B2 (en) 2010-05-20 2016-06-07 Kandou Labs, S.A. Methods and systems for energy-efficient communications interface
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US9432082B2 (en) 2014-07-17 2016-08-30 Kandou Labs, S.A. Bus reversable orthogonal differential vector signaling codes
KR102243423B1 (ko) 2014-07-21 2021-04-22 칸도우 랩스 에스에이 다분기 데이터 전송
CN106576087B (zh) 2014-08-01 2019-04-12 康杜实验室公司 带内嵌时钟的正交差分向量信令码
US9674014B2 (en) 2014-10-22 2017-06-06 Kandou Labs, S.A. Method and apparatus for high speed chip-to-chip communications
US9832046B2 (en) 2015-06-26 2017-11-28 Kandou Labs, S.A. High speed communications system
US9557760B1 (en) 2015-10-28 2017-01-31 Kandou Labs, S.A. Enhanced phase interpolation circuit
US9577815B1 (en) 2015-10-29 2017-02-21 Kandou Labs, S.A. Clock data alignment system for vector signaling code communications link
US10055372B2 (en) 2015-11-25 2018-08-21 Kandou Labs, S.A. Orthogonal differential vector signaling codes with embedded clock
CN108781060B (zh) 2016-01-25 2023-04-14 康杜实验室公司 具有增强的高频增益的电压采样驱动器
US10003454B2 (en) 2016-04-22 2018-06-19 Kandou Labs, S.A. Sampler with low input kickback
WO2017185072A1 (en) 2016-04-22 2017-10-26 Kandou Labs, S.A. High performance phase locked loop
US10056903B2 (en) 2016-04-28 2018-08-21 Kandou Labs, S.A. Low power multilevel driver
US10153591B2 (en) 2016-04-28 2018-12-11 Kandou Labs, S.A. Skew-resistant multi-wire channel
WO2017189931A1 (en) 2016-04-28 2017-11-02 Kandou Labs, S.A. Vector signaling codes for densely-routed wire groups
BE1024217B1 (nl) * 2016-05-17 2017-12-19 Icsense Nv Analoog schakelcircuit
US9906358B1 (en) 2016-08-31 2018-02-27 Kandou Labs, S.A. Lock detector for phase lock loop
US10411922B2 (en) 2016-09-16 2019-09-10 Kandou Labs, S.A. Data-driven phase detector element for phase locked loops
US10200188B2 (en) 2016-10-21 2019-02-05 Kandou Labs, S.A. Quadrature and duty cycle error correction in matrix phase lock loop
US10200218B2 (en) 2016-10-24 2019-02-05 Kandou Labs, S.A. Multi-stage sampler with increased gain
US10372665B2 (en) 2016-10-24 2019-08-06 Kandou Labs, S.A. Multiphase data receiver with distributed DFE
US10116468B1 (en) 2017-06-28 2018-10-30 Kandou Labs, S.A. Low power chip-to-chip bidirectional communications
US10686583B2 (en) 2017-07-04 2020-06-16 Kandou Labs, S.A. Method for measuring and correcting multi-wire skew
US10203226B1 (en) 2017-08-11 2019-02-12 Kandou Labs, S.A. Phase interpolation circuit
US10496583B2 (en) 2017-09-07 2019-12-03 Kandou Labs, S.A. Low power multilevel driver for generating wire signals according to summations of a plurality of weighted analog signal components having wire-specific sub-channel weights
US10326623B1 (en) 2017-12-08 2019-06-18 Kandou Labs, S.A. Methods and systems for providing multi-stage distributed decision feedback equalization
US10554380B2 (en) 2018-01-26 2020-02-04 Kandou Labs, S.A. Dynamically weighted exclusive or gate having weighted output segments for phase detection and phase interpolation
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