JP2016192541A - SiCベースの超接合半導体装置 - Google Patents
SiCベースの超接合半導体装置 Download PDFInfo
- Publication number
- JP2016192541A JP2016192541A JP2016020504A JP2016020504A JP2016192541A JP 2016192541 A JP2016192541 A JP 2016192541A JP 2016020504 A JP2016020504 A JP 2016020504A JP 2016020504 A JP2016020504 A JP 2016020504A JP 2016192541 A JP2016192541 A JP 2016192541A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- region
- semiconductor region
- semiconductor body
- doped
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 385
- 239000002019 doping agent Substances 0.000 claims abstract description 50
- 238000009792 diffusion process Methods 0.000 claims abstract description 37
- 239000000463 material Substances 0.000 claims abstract description 37
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 21
- 239000010703 silicon Substances 0.000 claims abstract description 21
- 230000000295 complement effect Effects 0.000 claims abstract description 12
- 150000002500 ions Chemical class 0.000 claims description 48
- 238000002513 implantation Methods 0.000 claims description 46
- 238000000034 method Methods 0.000 claims description 32
- 238000004519 manufacturing process Methods 0.000 claims description 30
- 239000007943 implant Substances 0.000 claims description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 14
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 14
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 14
- 230000001747 exhibiting effect Effects 0.000 claims description 11
- 230000007704 transition Effects 0.000 claims description 8
- 229910002601 GaN Inorganic materials 0.000 claims description 7
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 7
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 7
- 230000008859 change Effects 0.000 claims description 6
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 230000009467 reduction Effects 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 229910052799 carbon Inorganic materials 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 239000010949 copper Substances 0.000 claims description 2
- 229910002804 graphite Inorganic materials 0.000 claims description 2
- 239000010439 graphite Substances 0.000 claims description 2
- 239000011133 lead Substances 0.000 claims description 2
- 229910052750 molybdenum Inorganic materials 0.000 claims description 2
- 239000011733 molybdenum Substances 0.000 claims description 2
- 235000012239 silicon dioxide Nutrition 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- 239000010936 titanium Substances 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 230000000873 masking effect Effects 0.000 claims 2
- 238000007740 vapor deposition Methods 0.000 claims 1
- 239000000758 substrate Substances 0.000 description 12
- 239000000370 acceptor Substances 0.000 description 7
- 230000008569 process Effects 0.000 description 7
- 238000000407 epitaxy Methods 0.000 description 6
- 238000002347 injection Methods 0.000 description 6
- 239000007924 injection Substances 0.000 description 6
- 230000007423 decrease Effects 0.000 description 2
- JJWKPURADFRFRB-UHFFFAOYSA-N carbonyl sulfide Chemical compound O=C=S JJWKPURADFRFRB-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
- H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
- H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
- H01L21/0465—Making n or p doped regions or layers, e.g. using diffusion using ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/2654—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds
- H01L21/26546—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Ceramic Engineering (AREA)
- Composite Materials (AREA)
- Electrodes Of Semiconductors (AREA)
- Recrystallisation Techniques (AREA)
- Inorganic Chemistry (AREA)
Abstract
【解決手段】半導体装置1は、シリコンのドーパント拡散係数より小さいドーパント拡散係数を示す半導体ボディ材料を含む半導体ボディ11と、第1の導電型のドーパントでドープされるとともに延伸方向Bに沿って半導体ボディ11中に延伸する円柱形状を示す、それぞれの幅Dが延伸方向Bに沿って連続的に増加する、少なくとも1つの第1の半導体領域111−1、111−2と、半導体ボディ11内に含まれる、第1の半導体領域に隣接するように配置されるとともに、第1の導電型と相補的な第2の導電型のドーパントでドープされる、少なくとも1つの第2の半導体領域112とを含む。
【選択図】図1
Description
11 半導体ボディ
11−1 表面
11−2 ノンドープまたは弱ドープ領域
11−3 基材領域
11−4 ドリフト容積
11−5 ドープ層
31 第1の注入
32 第2の注入
33 エネルギー拡散器アセンブリ
33−1 入口の第1の点
33−2 入口の第2の点
35−1 第1のマスク
35−2 第2のマスク
35−11 第1のマスク要素
35−12 第1の開口
35−21 第2のマスク要素
35−22 第2の開口
36−1 第1のイオン
36−2 第2のイオン
37−2 第2の経路
71 半導体装置
72 第2の気泡
73 第1の気泡
74 注入工程
75 半導体領域
76 半導体領域
81 半導体装置
82 トレンチ
83 マスク
84 トレンチ充填材
111−1 第1の半導体領域
111−2 第1の半導体領域
111−11 近位端
111−12 遠位端
111−13 接合領域
111−21 近位端
111−22 遠位端
111−23 接合領域
112 第2の半導体領域
331 支持層
331−1 レセプタ側
332 拡散器構造
332−1 拡散器素子
332−2 拡散器素子
332−3 拡散器素子
332−4 拡散器素子
711 半導体基材領域
712 ドープ半導体領域
713 ノンドープまたは弱ドープエピタキシャル層
714 マスク
811 半導体基材領域
812 ドープ半導体領域
A 距離
b1 延伸深さ
b2 延伸深さ
c1 濃度プロファイル
d1 近位幅
d2 遠位幅
B 延伸方向
D 幅
E1 第1のエネルギー
E1’ 第1の低下エネルギー
E2 第2のエネルギー
E2’ 第2の低下エネルギー
α 傾斜角
β 延伸角
Claims (20)
- − シリコンのドーパント拡散係数より小さいドーパント拡散係数を示す半導体ボディ材料を含む半導体ボディ(11)と、
− 第1の導電型のドーパントでドープされるとともに延伸方向(B)に沿って前記半導体ボディ(11)中に延伸する円柱形状を示す少なくとも1つの第1の半導体領域(111−1、111−2)であって、前記少なくとも1つの第1の半導体領域(111−1、111−2)のそれぞれの幅(D)が前記延伸方向(B)に沿って連続的に増加する、少なくとも1つの第1の半導体領域(111−1、111−2)と、
− 前記半導体ボディ(11)内に含まれる少なくとも1つの第2の半導体領域(112)であって、前記少なくとも1つの第1の半導体領域(111−1、111−2)に隣接するように配置されるとともに前記第1の導電型と相補的な第2の導電型のドーパントでドープされる、少なくとも1つの第2の半導体領域(112)とを含む半導体装置(1)。 - 前記少なくとも1つの第1の半導体領域(111−1、111−2)は近位幅(d1)を示す近位端(111−11、111−21)と遠位幅(d2)を示す遠位端(111−12、111−22)とを含み、
前記少なくとも1つの第1の半導体領域(111−1、111−2)の前記延伸方向(B)に沿った前記近位端(111−11、111−21)と前記遠位端(111−12、111−22)との間の他の全ての位置における幅(D)は前記近位幅(d1)より大きく、前記遠位幅(d2)より小さい、請求項1に記載の半導体装置(1)。 - 前記少なくとも1つの第1の半導体領域(111−1、111−2)の前記それぞれの幅(D)の変化率が、延伸角(β)により与えられ、前記延伸角(β)は前記延伸方向(B)と前記少なくとも1つの第1の半導体領域(111−1、111−2)の接合領域(111−13、111−23)との仮想交差点における交角と同一である、請求項1または2に記載の半導体装置(1)。
- 前記延伸角(β)は0.1°〜10°の範囲内である、請求項3に記載の半導体装置(1)。
- − シリコンのドーパント拡散係数より小さいドーパント拡散係数を示す半導体ボディ材料を含む半導体ボディ(11)と、
− 前記半導体ボディ(11)内に含まれる少なくとも1つの第1の半導体領域(111−1、111−2)であって、注入された第1の導電型のドーパントでドープされるとともに、延伸方向(B)に沿った半導体ボディ(11)中に延伸する円柱形状を示す、少なくとも1つの第1の半導体領域(111−1、111−2)と、
− 前記半導体ボディ(11)内に含まれる少なくとも1つの第2の半導体領域(112)であって、前記少なくとも1つの第1の半導体領域(111−1、111−2)に隣接するように配置されるとともに前記第1の導電型と相補的な注入された第2の導電型のドーパントでドープされる、少なくとも1つの第2の半導体領域(112)とを含む半導体装置(1)であって、
前記延伸方向(B)に垂直な方向の前記第1の半導体領域(111−1、111−2)と前記第2の半導体領域(112)との遷移部が、前記半導体装置(1)の垂直断面内に、前記延伸方向(B)に沿った前記第1の半導体領域(111−1、111−2)の総延長の少なくとも50%に沿って直線(111−13、111−23)を形成する、半導体装置(1)。 - 前記延伸方向(B)に沿った前記第1の半導体領域(111−1、111−2)のドーピング濃度は、前記第1の半導体領域(111−1、111−2)の総延長の少なくとも10%に沿った固定値から30%未満だけ逸脱する、請求項1から5のいずれか一項に記載の半導体装置(1)。
- 前記半導体ボディ材料の前記ドーパント拡散係数はアクセプタ拡散係数またはドナー拡散係数のいずれかである、請求項1から6のいずれか一項に記載の半導体装置(1)。
- 前記半導体ボディ(11)の前記半導体ボディ材料は、炭化珪素、窒化ガリウム、窒化アルミニウム、シリコンのドーパント拡散係数より少なくとも2桁低いドーパント拡散係数を有する半導体材料のうちの少なくとも1つを含む、請求項1から7のいずれか一項に記載の半導体装置(1)。
- 前記少なくとも1つの第1の半導体領域(111−1、111−2)は第1の注入イオンの少なくとも1つの第1の注入(31)を適用することにより生成され、前記少なくとも1つの第2の半導体領域(112)は第2の注入イオンの少なくとも1つの第2の注入(32)を適用することにより生成される、請求項1から8のいずれか一項に記載の半導体装置(1)。
- 前記少なくとも1つの第1の半導体領域(111−1、111−2)と前記少なくとも1つの第2の半導体領域(112)とは超接合構造を示すドリフト容積(11−4)を形成する、請求項1から9のいずれか一項に記載の半導体装置(1)。
- 半導体装置(1)の製造方法であって、
− シリコンのドーパント拡散係数より小さいドーパント拡散係数を示す半導体ボディ材料を含む半導体ボディ(11)を設ける工程と、
− 第1の導電型のドーパントでドープされた少なくとも1つの第1の半導体領域(111−1、111−2)を前記半導体ボディ(11)内に生成する工程であって、第1の注入イオンの第1の注入(31)を適用する工程を含む、工程と、
− 前記少なくとも1つの第1の半導体領域(111−1、111−2)に隣接するとともに前記第1の導電型と相補的な第2の導電型のドーパントでドープされた少なくとも1つの第2の半導体領域(112)を前記半導体ボディ(11)内に生成する工程であって、第2の注入イオンの第2の注入(32)を適用する工程を含む、工程とを含む方法。 - − 注入装置と半導体ボディ(11)との間にエネルギー拡散器アセンブリ(33)を配置する工程であって、前記エネルギー拡散器アセンブリ(33)は、注入イオンを受け取るように構成され、かつ前記出力注入イオンが、前記エネルギー拡散器アセンブリ(33)に入る際のそのエネルギーと比較して低下されたエネルギーを示すように、受け取った注入イオンを出力するように構成され、前記それぞれのエネルギーの低下量は前記エネルギー拡散器アセンブリ(33)に入る点および/または角度に依存する、工程と、
− 前記第1の注入イオンと前記第2の注入イオンとの少なくとも1つが前記半導体ボディ(11)に入る前に前記エネルギー拡散器アセンブリ(33)を横断するように前記第1の注入(31)および前記第2の注入(32)を適用する工程とをさらに含む請求項11に記載の方法。 - 第1のマスク(35−1)により前記半導体ボディ(11)の表面(11−1)をマスクする工程であって、前記第1の注入(31)は前記表面(11−1)が前記第1のマスク(35−1)でマスクされている状態で適用される、工程をさらに含む請求項11または12に記載の方法。
- 前記第2の注入(32)を適用する前に前記第1のマスク(35−1)を除去する工程をさらに含む請求項13に記載の方法。
- 第2のマスク(35−2)により前記半導体ボディ(11)の前記表面(11−1)をマスクする工程であって、前記第2の注入(32)は前記表面(11−1)が前記第2のマスク(35−2)でマスクされた状態で適用され、前記第2のマスク(35−2)は前記第1のマスク(35−1)の構造と相補的な構造を示す、工程をさらに含む請求項13または14に記載の方法。
- 前記エネルギー拡散器アセンブリ(33)を生成するために前記半導体ボディ(11)、または前記第1のマスク(35−1)、または前記第2のマスク(35−2)上にエネルギー拡散器材料を蒸着する工程であって、前記エネルギー拡散器材料は、シリコン、二酸化ケイ素、アルミニウム、炭化珪素、グラファイト、炭素、タングステン、モリブデン、チタン、鉛、銅のうちの少なくとも1つを含む、工程をさらに含む請求項12、または請求項12および13、または請求項12および15に記載の方法。
- 前記半導体ボディ(11)の前記半導体ボディ材料は、炭化珪素、窒化ガリウム、窒化アルミニウム、シリコンのドーパント拡散係数より少なくとも2桁低いドーパント拡散係数を示す半導体材料のうちの少なくとも1つを含む、請求項11から16のいずれか一項に記載の方法。
- 前記半導体ボディ(11)は当初ノンドープまたは弱ドープである領域(11−2)を含み、前記少なくとも1つの第1の半導体領域(111−1、111−2)と前記少なくとも1つの第2の半導体領域(112)とは前記当初ノンドープまたは弱ドープである領域(11−2)内に生成される、請求項11から17のいずれか一項に記載の方法。
- 前記当初ノンドープまたは弱ドープである領域(11−2)は、炭化珪素層、窒化ガリウム層、窒化アルミニウム層、シリコンのドーパント拡散係数より少なくとも2桁低いドーパント拡散係数を示す半導体材料の層のうちの1つである、請求項18に記載の方法。
- 前記第1の注入(31)および前記第2の注入(32)は、前記少なくとも1つの第1の半導体領域(111−1、111−2)と前記少なくとも1つの第2の半導体領域(112)とにより前記半導体ボディ(11)内に超接合構造を確立するために適用される、請求項11から19のいずれか一項に記載の方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102015202121.1A DE102015202121B4 (de) | 2015-02-06 | 2015-02-06 | SiC-basierte Supersperrschicht-Halbleitervorrichtungen und Verfahren zur Herstellung dieser |
DE102015202121.1 | 2015-02-06 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2019190772A Division JP7111681B2 (ja) | 2015-02-06 | 2019-10-18 | SiCベースの超接合半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2016192541A true JP2016192541A (ja) | 2016-11-10 |
JP6647897B2 JP6647897B2 (ja) | 2020-02-14 |
Family
ID=56498564
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2016020504A Active JP6647897B2 (ja) | 2015-02-06 | 2016-02-05 | SiCベースの超接合半導体装置 |
JP2019190772A Active JP7111681B2 (ja) | 2015-02-06 | 2019-10-18 | SiCベースの超接合半導体装置 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2019190772A Active JP7111681B2 (ja) | 2015-02-06 | 2019-10-18 | SiCベースの超接合半導体装置 |
Country Status (4)
Country | Link |
---|---|
US (2) | US9859361B2 (ja) |
JP (2) | JP6647897B2 (ja) |
CN (1) | CN105870162A (ja) |
DE (1) | DE102015202121B4 (ja) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019083317A (ja) * | 2017-10-27 | 2019-05-30 | インフィニオン テクノロジーズ アクチエンゲゼルシャフトInfineon Technologies AG | フィールドゾーンを含む終端構造を有する半導体デバイスおよびその製造方法 |
JP2019102550A (ja) * | 2017-11-29 | 2019-06-24 | トヨタ自動車株式会社 | 半導体基板の製造方法 |
JP2019165165A (ja) * | 2018-03-20 | 2019-09-26 | 株式会社デンソー | 炭化珪素半導体装置およびその製造方法 |
JP2022532048A (ja) * | 2019-05-16 | 2022-07-13 | エムアイツー‐ファクトリー ジーエムビーエイチ | 半導体部品および半導体部品を製造するための装置 |
JP2022532999A (ja) * | 2019-05-15 | 2022-07-21 | エムアイツー‐ファクトリー ジーエムビーエイチ | 基板に粒子を注入するための装置および方法 |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11075264B2 (en) * | 2016-05-31 | 2021-07-27 | Cree, Inc. | Super junction power semiconductor devices formed via ion implantation channeling techniques and related methods |
DE102016110429A1 (de) | 2016-06-06 | 2017-12-07 | Infineon Technologies Ag | Energiefilter zum Verarbeiten einer Leistungshalbleitervorrichtung |
DE102016110523B4 (de) | 2016-06-08 | 2023-04-06 | Infineon Technologies Ag | Verarbeiten einer Leistungshalbleitervorrichtung |
DE102016122791B3 (de) | 2016-11-25 | 2018-05-30 | mi2-factory GmbH | Ionenimplantationsanlage, Filterkammer und Implantationsverfahren unter Einsatz eines Energiefilterelements |
US11380803B2 (en) | 2017-10-30 | 2022-07-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device structure and method for forming the same |
US10957759B2 (en) * | 2018-12-21 | 2021-03-23 | General Electric Company | Systems and methods for termination in silicon carbide charge balance power devices |
US11171248B2 (en) | 2019-02-12 | 2021-11-09 | Semiconductor Components Industries, Llc | Schottky rectifier with surge-current ruggedness |
DE102019114312A1 (de) | 2019-05-28 | 2020-12-03 | Infineon Technologies Ag | Siliziumcarbid-vorrichtung mit kompensationsgebiet und herstellungsverfahren |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001015448A (ja) * | 1999-06-28 | 2001-01-19 | Toshiba Corp | 半導体装置の製造方法 |
JP2001522145A (ja) * | 1997-11-03 | 2001-11-13 | インフィネオン テクノロジース アクチエンゲゼルシャフト | 半導体構成素子のための耐高圧縁部構造 |
JP2003069040A (ja) * | 2001-08-29 | 2003-03-07 | Denso Corp | 炭化珪素半導体装置およびその製造方法 |
JP2003273355A (ja) * | 2002-03-18 | 2003-09-26 | Toshiba Corp | 半導体素子およびその製造方法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2078441A (en) * | 1980-06-17 | 1982-01-06 | Westinghouse Electric Corp | Forming impurity regions in semiconductor bodies by high energy ion irradiation |
JP3634830B2 (ja) * | 2002-09-25 | 2005-03-30 | 株式会社東芝 | 電力用半導体素子 |
JP4193596B2 (ja) * | 2003-06-09 | 2008-12-10 | 三菱電機株式会社 | 炭化珪素半導体装置の製造方法 |
FR2858694B1 (fr) | 2003-08-07 | 2006-08-18 | Commissariat Energie Atomique | Procede de realisation de motifs a flancs inclines par photolithographie |
JP2007523440A (ja) * | 2004-02-18 | 2007-08-16 | 学校法人早稲田大学 | イオン注入方法及び装置 |
JP5188037B2 (ja) * | 2006-06-20 | 2013-04-24 | 株式会社東芝 | 半導体装置 |
JP2007311669A (ja) | 2006-05-22 | 2007-11-29 | Toshiba Corp | 半導体装置及びその製造方法 |
US20120273916A1 (en) * | 2011-04-27 | 2012-11-01 | Yedinak Joseph A | Superjunction Structures for Power Devices and Methods of Manufacture |
US8806615B2 (en) | 2010-11-04 | 2014-08-12 | Mcafee, Inc. | System and method for protecting specified data combinations |
-
2015
- 2015-02-06 DE DE102015202121.1A patent/DE102015202121B4/de active Active
-
2016
- 2016-02-04 CN CN201610078275.6A patent/CN105870162A/zh active Pending
- 2016-02-05 JP JP2016020504A patent/JP6647897B2/ja active Active
- 2016-02-05 US US15/016,680 patent/US9859361B2/en active Active
-
2017
- 2017-12-26 US US15/854,341 patent/US10541301B2/en active Active
-
2019
- 2019-10-18 JP JP2019190772A patent/JP7111681B2/ja active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001522145A (ja) * | 1997-11-03 | 2001-11-13 | インフィネオン テクノロジース アクチエンゲゼルシャフト | 半導体構成素子のための耐高圧縁部構造 |
JP2001015448A (ja) * | 1999-06-28 | 2001-01-19 | Toshiba Corp | 半導体装置の製造方法 |
JP2003069040A (ja) * | 2001-08-29 | 2003-03-07 | Denso Corp | 炭化珪素半導体装置およびその製造方法 |
JP2003273355A (ja) * | 2002-03-18 | 2003-09-26 | Toshiba Corp | 半導体素子およびその製造方法 |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019083317A (ja) * | 2017-10-27 | 2019-05-30 | インフィニオン テクノロジーズ アクチエンゲゼルシャフトInfineon Technologies AG | フィールドゾーンを含む終端構造を有する半導体デバイスおよびその製造方法 |
JP7271133B2 (ja) | 2017-10-27 | 2023-05-11 | インフィニオン テクノロジーズ アクチエンゲゼルシャフト | フィールドゾーンを含む終端構造を有する半導体デバイスおよびその製造方法 |
JP2019102550A (ja) * | 2017-11-29 | 2019-06-24 | トヨタ自動車株式会社 | 半導体基板の製造方法 |
JP2019165165A (ja) * | 2018-03-20 | 2019-09-26 | 株式会社デンソー | 炭化珪素半導体装置およびその製造方法 |
JP7095342B2 (ja) | 2018-03-20 | 2022-07-05 | 株式会社デンソー | 炭化珪素半導体装置およびその製造方法 |
JP2022532999A (ja) * | 2019-05-15 | 2022-07-21 | エムアイツー‐ファクトリー ジーエムビーエイチ | 基板に粒子を注入するための装置および方法 |
JP7210071B2 (ja) | 2019-05-15 | 2023-01-23 | エムアイツー‐ファクトリー ジーエムビーエイチ | 基板に粒子を注入するための装置および方法 |
JP2022532048A (ja) * | 2019-05-16 | 2022-07-13 | エムアイツー‐ファクトリー ジーエムビーエイチ | 半導体部品および半導体部品を製造するための装置 |
JP7405453B2 (ja) | 2019-05-16 | 2023-12-26 | エムアイツー‐ファクトリー ジーエムビーエイチ | 半導体部品を製造するための方法 |
Also Published As
Publication number | Publication date |
---|---|
US9859361B2 (en) | 2018-01-02 |
CN105870162A (zh) | 2016-08-17 |
US10541301B2 (en) | 2020-01-21 |
US20160233295A1 (en) | 2016-08-11 |
US20180138266A1 (en) | 2018-05-17 |
JP6647897B2 (ja) | 2020-02-14 |
DE102015202121B4 (de) | 2017-09-14 |
JP7111681B2 (ja) | 2022-08-02 |
DE102015202121A1 (de) | 2016-08-11 |
JP2020038975A (ja) | 2020-03-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP7111681B2 (ja) | SiCベースの超接合半導体装置 | |
US10325996B2 (en) | Method for producing a doped semiconductor layer | |
JP6109930B2 (ja) | 適応的電荷平衡エッジ終端 | |
KR101709565B1 (ko) | 초접합 mosfet 디바이스를 위한 에지 종단 | |
US9905555B2 (en) | Semiconductor device and semiconductor device manufacturing method | |
US9418851B2 (en) | Method for manufacturing a semiconductor device | |
CN110034173B (zh) | 宽带隙半导体器件和形成宽带隙半导体器件的方法 | |
CN105097934B (zh) | 半导体器件及其制造方法 | |
US9666696B2 (en) | Method of manufacturing a vertical junction field effect transistor | |
JP6861171B2 (ja) | 炭化ケイ素超接合パワーデバイスの活性領域設計および対応する方法 | |
US20120299094A1 (en) | Semiconductor device having a super junction structure and method of manufacturing the same | |
JP6782529B2 (ja) | 半導体装置 | |
US20200381253A1 (en) | Silicon carbide device with compensation region and method of manufacturing | |
US9722041B2 (en) | Breakdown voltage blocking device | |
US9825165B2 (en) | Charge-compensation device | |
US20180061979A1 (en) | Method of Manufacturing a Superjunction Semiconductor Device and Superjunction Semiconductor Device | |
CN109219889B (zh) | 半导体装置和半导体装置的制造方法 | |
JP2014120685A (ja) | 半導体装置 | |
WO2019000703A1 (zh) | 一种叠层电场调制高压mosfet结构及其制作方法 | |
JP6809071B2 (ja) | 半導体装置および半導体装置の製造方法 | |
KR101121574B1 (ko) | 전하 균형 전력 디바이스 및 그 제조 방법 | |
JP6777198B2 (ja) | 半導体装置 | |
CN221928090U (zh) | 电子装置 | |
US9184250B1 (en) | Semiconductor arrangement and formation thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20160606 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20170710 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20170718 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20171011 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20171215 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20180117 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20180130 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20180529 |
|
C60 | Trial request (containing other claim documents, opposition documents) |
Free format text: JAPANESE INTERMEDIATE CODE: C60 Effective date: 20180529 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20180606 |
|
C21 | Notice of transfer of a case for reconsideration by examiners before appeal proceedings |
Free format text: JAPANESE INTERMEDIATE CODE: C21 Effective date: 20180612 |
|
A912 | Re-examination (zenchi) completed and case transferred to appeal board |
Free format text: JAPANESE INTERMEDIATE CODE: A912 Effective date: 20180706 |
|
C211 | Notice of termination of reconsideration by examiners before appeal proceedings |
Free format text: JAPANESE INTERMEDIATE CODE: C211 Effective date: 20180710 |
|
C22 | Notice of designation (change) of administrative judge |
Free format text: JAPANESE INTERMEDIATE CODE: C22 Effective date: 20181106 |
|
C22 | Notice of designation (change) of administrative judge |
Free format text: JAPANESE INTERMEDIATE CODE: C22 Effective date: 20190402 |
|
C22 | Notice of designation (change) of administrative judge |
Free format text: JAPANESE INTERMEDIATE CODE: C22 Effective date: 20190416 |
|
C22 | Notice of designation (change) of administrative judge |
Free format text: JAPANESE INTERMEDIATE CODE: C22 Effective date: 20190528 |
|
C13 | Notice of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: C13 Effective date: 20190618 |
|
C22 | Notice of designation (change) of administrative judge |
Free format text: JAPANESE INTERMEDIATE CODE: C22 Effective date: 20190709 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20190912 |
|
C22 | Notice of designation (change) of administrative judge |
Free format text: JAPANESE INTERMEDIATE CODE: C22 Effective date: 20191015 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20191018 |
|
C23 | Notice of termination of proceedings |
Free format text: JAPANESE INTERMEDIATE CODE: C23 Effective date: 20191119 |
|
C03 | Trial/appeal decision taken |
Free format text: JAPANESE INTERMEDIATE CODE: C03 Effective date: 20191217 |
|
C30A | Notification sent |
Free format text: JAPANESE INTERMEDIATE CODE: C3012 Effective date: 20191217 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20200115 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6647897 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |