JP2016048731A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP2016048731A JP2016048731A JP2014173210A JP2014173210A JP2016048731A JP 2016048731 A JP2016048731 A JP 2016048731A JP 2014173210 A JP2014173210 A JP 2014173210A JP 2014173210 A JP2014173210 A JP 2014173210A JP 2016048731 A JP2016048731 A JP 2016048731A
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- silicon nitride
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Abstract
【解決手段】一実施の形態の半導体装置の製造方法において、窒化シリコン膜からなるキャップ絶縁膜上にレジストパターンを形成する際に、レジストパターンは、化学増幅型レジストの塗布S34、露光S36、現像処理S38の工程により形成する。そして、化学増幅型レジストは、窒化シリコン膜からなるキャップ絶縁膜の表面に直接、接するように塗布し、化学増幅型レジストの塗布前に、窒化シリコン膜からなるキャップ絶縁膜の表面に有機酸前処理S32を施す。
【選択図】図23
Description
<半導体チップのレイアウト構成例>
本実施の形態1における不揮発性メモリを有する半導体装置について図面を参照しながら説明する。まず、不揮発性メモリを含むシステムが形成された半導体装置(半導体チップ)のレイアウト構成について説明する。図1は、本実施の形態1における半導体チップCHPのレイアウト構成例を示す図である。図1において、半導体チップCHPは、CPU(Central Processing Unit)1、RAM(Random Access Memory)2、アナログ回路3、EEPROM(Electrically Erasable Programmable Read Only Memory)4、フラッシュメモリ5およびI/O(Input/Output)回路6を有し、半導体集積回路装置を構成している。
図2は、本実施の形態1における半導体装置のデバイス構造例について説明する図である。図2では、メモリ形成領域に形成されている不揮発性メモリのデバイス構造と、周辺回路領域に形成されている高耐圧MISFET(Metal Insulator Semiconductor Field Effect Transistor)のデバイス構造とが図示されている。
以上のようにして、本実施の形態1における半導体装置が構成されており、次に、本実施の形態1における半導体装置の製造方法について、図面を参照しながら説明する。図3および図4は、実施の形態1の半導体装置の製造工程の一部を示すプロセスフロー図である。図5〜図22は、本実施の形態1における半導体装置の製造工程中の断面図であり、図2に示される半導体装置の製造工程に対応した図となっている。
次に、本発明者の検討例である半導体装置の製造方法について説明する。図25から図27は、検討例の半導体装置の製造工程中の断面図である。
次に、本実施の形態の主要な特徴と効果について説明する。
上記実施の形態1における有機酸前処理に関する変形例を以下に説明する。有機酸前処理以外の部分は、上記実施の形態1と同様である。
変形例の場合、薬液Bの粘度を薬液Aよりも高くできるため、半導体ウエハの主面に薬液Bを塗布膜として均一に塗り広げることが出来、半導体ウエハの面内における有機酸前処理のバラツキを低減することができる。ただし、変形例の場合、熱処理後に高分子有機化合物を酢酸ブチル等のシンナーで溶解除去する必要がある。
本実施の形態2は、上記実施の形態1の半導体装置の周辺回路形成領域における素子分離膜STIの形成工程を示すものである。図28から図32は、本実施の形態2の半導体装置の製造工程中の断面図である。図28から図32は、実施の形態1における、図3のステップS1およびステップS2の工程に対応している。例えば、図28に示すように半導体基板1Sには、活性領域ACTと素子分離領域ISOが設けられており、素子分離領域ISOには素子分離膜STIが、活性領域ACTには、例えば、高耐圧MISFETが形成される。
S34 レジスト塗布
S36 露光
S38 現像
Claims (20)
- (a)半導体基板上に窒化シリコン膜を形成する工程、
(b)前記窒化シリコン膜の主面を有機酸処理する工程、
(c)前記窒化シリコン膜の前記主面上に、化学増幅型レジストを用いて、所定のパターンを有するレジストマスクを形成する工程、
(d)前記レジストマスクを用いて、前記窒化シリコン膜にエッチング処理を施す工程、
を有し、
前記窒化シリコン膜の前記主面に接するように前記化学増幅型レジストを形成する、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記(c)工程は、
(c−1)前記窒化シリコン膜の前記主面上に、前記化学増幅型レジストを塗布する工程、
(c−2)前記化学増幅型レジストに対して部分的に紫外光を照射する露光工程、
(c−3)前記紫外光が照射された光照射部分の前記化学増幅型レジストを現像液で除去する現像工程、
を有する、半導体装置の製造方法。 - 請求項2に記載の半導体装置の製造方法において、
前記現像液に含まれる各金属単体の金属含有量は、2wtppt以下である、半導体装置の製造方法。 - 請求項2に記載の半導体装置の製造方法において、
前記紫外光は、KrFエキシマレーザー光またはArFエキシマレーザー光である、半導体装置の製造方法。 - 請求項2に記載の半導体装置の製造方法において、
前記(b)工程と前記(c)工程との間に、さらに、
(e)前記窒化シリコン膜の前記主面に対し、HMDS処理を施す工程、
を有する、半導体装置の製造方法。 - 請求項2に記載の半導体装置の製造方法において、
前記(b)工程は、
(b−1)第1有機酸と第1有機溶媒とを混合した第1薬液を、前記窒化シリコン膜の前記主面に供給する工程、
(b−2)前記半導体基板に対して、第1熱処理を施す工程、
を有する、半導体装置の製造方法。 - 請求項2に記載の半導体装置の製造方法において、
前記(b)工程は、
(b−3)第2有機酸と、高分子有機化合物と、第2有機溶媒と、を混合した第2薬液を、前記窒化シリコン膜の前記主面に供給する工程、
(b−4)前記半導体基板に対して、第2熱処理を施す工程、
(b−5)前記高分子有機化合物をシンナーで除去する工程、
を有する、半導体装置の製造方法。 - 請求項2に記載の半導体装置の製造方法において、
前記(a)工程と前記(b)工程との間に、さらに、
(f)前記窒化シリコン膜の前記主面を、SPM洗浄、APM洗浄、DFM洗浄、HPM洗浄、または、純水洗浄する工程、
を有する半導体装置の製造方法。 - 請求項2に記載の半導体装置の製造方法において、
前記(c−2)工程と前記(c−3)工程との間に、さらに、
(c−4)前記化学増幅型レジストの前記光照射部分における脱保護反応を進行させるために、前記半導体基板に第3熱処理を施す工程、
を有する半導体装置の製造方法。 - 請求項2に記載の半導体装置の製造方法において、
前記エッチング処理は、異方性ドライエッチングである、半導体装置の製造方法。 - メモリセル形成領域にコントロールゲート電極とメモリゲート電極を有する不揮発性メモリセルと、周辺回路形成領域にゲート電極を有するMISFETと、を有する半導体装置体装置の製造方法であって、
(a)前記メモリセル形成領域と前記周辺回路形成領域を有する半導体基板の上に、第1ポリシリコン膜、前記第1ポリシリコン膜上に、主面を有する第1窒化シリコン膜を形成する工程、
(b)前記周辺回路形成領域を第1レジストマスクで覆った状態で、前記メモリセル形成領域の前記第1窒化シリコン膜と前記第1ポリシリコン膜とをパターニングすることにより、前記メモリセル形成領域に前記コントロールゲート電極を形成する工程、
(c)前記メモリセル形成領域および前記周辺回路形成領域において、前記第1窒化シリコン膜の前記主面を有機酸処理する工程、
(d)前記第1窒化シリコン膜の前記主面上に、化学増幅型レジストを用いて、前記メモリセル形成領域を覆い、前記周辺回路形成領域を露出する第2レジストマスクを形成する工程、
(e)前記第2レジストマスクを用いて、前記周辺回路形成領域の前記第1窒化シリコン膜に第1異方性ドライエッチング処理を施し、前記周辺回路形成領域の前記第1窒化シリコン膜を除去する工程、
(f)前記メモリセル形成領域および前記周辺回路形成領域に、第1酸化シリコン膜、第2窒化シリコン膜、第2酸化シリコン膜、および、第2ポリシリコン膜を順次形成した後、前記第2ポリシリコン膜に第2異方性ドライエッチング処理を施し、前記メモリセル形成領域において、前記コントロールゲート電極の側壁に前記メモリゲート電極を形成し、前記周辺回路形成領域の前記第2ポリシリコン膜を除去する工程、
(g)前記メモリセル形成領域において、前記コントロールゲート電極で覆われていない領域の前記第2酸化シリコン膜および前記第2窒化シリコン膜を除去し、前記周辺回路形成領域において、前記第2酸化シリコン膜および前記第2窒化シリコン膜を除去する工程、
(h)前記メモリセル形成領域を覆う第3レジストマスクを用いて、前記周辺回路形成領域において、前記第1ポリシリコン膜に第3異方性ドライエッチングを施し、前記ゲート電極を形成する工程、
を有し、
前記第1窒化シリコン膜の前記主面に接するように前記化学増幅型レジストを形成する、半導体装置の製造方法。 - 請求項11に記載の半導体装置の製造方法において、
前記(d)工程は、
(d−1)前記第1窒化シリコン膜の前記主面上に、前記化学増幅型レジストを塗布する工程、
(d−2)前記化学増幅型レジストに対して部分的に紫外光を照射する露光工程、
(d−3)前記化学増幅型レジストの光照射部分における脱保護反応を進行させるために、前記半導体基板に第1熱処理を施す工程、
(d−4)前記紫外光が照射された前記光照射部分の前記化学増幅型レジストを現像液で除去する現像工程、
を有する、半導体装置の製造方法。 - 請求項12に記載の半導体装置の製造方法において、
前記現像液に含まれる各金属単体の金属含有量は、2wtppt以下である、半導体装置の製造方法。 - 請求項12に記載の半導体装置の製造方法において、
前記(c)工程は、
(c−1)第1有機酸と第1有機溶媒とを混合した第1薬液を、前記第1窒化シリコン膜の前記主面に供給する工程、
(c−2)前記半導体基板に対して、第2熱処理を施す工程、
を有する、半導体装置の製造方法。 - 請求項12に記載の半導体装置の製造方法において、
前記(c)工程は、
(c−3)第2有機酸と、高分子有機化合物と、第2有機溶媒と、を混合した第2薬液を、前記第1窒化シリコン膜の前記主面に供給する工程、
(c−4)前記半導体基板に対して、第3熱処理を施す工程、
(c−5)前記高分子有機化合物をシンナーで除去する工程、
を有する、半導体装置の製造方法。 - (a)活性領域と素子分離領域とを有する半導体基板の第1主面上に、第2主面を有する窒化シリコン膜を形成する工程、
(b)前記窒化シリコン膜の前記第2主面を有機酸処理する工程、
(c)前記窒化シリコン膜の前記第2主面上に、化学増幅型レジストを用いて、前記活性領域を覆い、前記素子分離領域を露出するレジストマスクを形成する工程、
(d)前記レジストマスクを用いて、前記窒化シリコン膜に第1ドライエッチング処理を施し、前記素子分離領域の前記窒化シリコン膜を除去する工程、
(e)前記半導体基板に第2ドライエッチング処理を施し、前記素子分離領域において、前記半導体基板の前記第1主面から深さ方向に溝を形成する工程、
(f)前記溝の内部および前記活性領域の前記窒化シリコン膜上に、前記溝が埋まるように絶縁膜を形成する工程、
(g)前記絶縁膜にCMP処理を施し、前記溝内に選択的に前記絶縁膜を残す工程、
(h)前記活性領域の前記窒化シリコン膜を除去した後、前記活性領域にMISFETを形成する工程、
を有し、
前記窒化シリコン膜の前記第2主面に接するように前記化学増幅型レジストを形成する、半導体装置の製造方法。 - 請求項16に記載の半導体装置の製造方法において、
前記(c)工程は、
(c−1)前記窒化シリコン膜の前記第2主面上に、前記化学増幅型レジストを塗布する工程、
(c−2)前記化学増幅型レジストに対して部分的に紫外光を照射する露光工程、
(c−3)前記化学増幅型レジストの光照射部分における脱保護反応を進行させるために、前記半導体基板に第1熱処理を施す工程、
(c−4)前記紫外光が照射された前記光照射部分の前記化学増幅型レジストを現像液で除去する現像工程、
を有する、半導体装置の製造方法。 - 請求項17に記載の半導体装置の製造方法において、
前記現像液に含まれる各金属単体の金属含有量は、2wtppt以下である、半導体装置の製造方法。 - 請求項17に記載の半導体装置の製造方法において、
前記(b)工程は、
(b−1)第1有機酸と第1有機溶媒とを混合した第1薬液を、前記窒化シリコン膜の前記第2主面に供給する工程、
(b−2)前記半導体基板に対して、第2熱処理を施す工程、
を有する、半導体装置の製造方法。 - 請求項17に記載の半導体装置の製造方法において、
前記(b)工程は、
(b−3)第2有機酸と、高分子有機化合物と、第2有機溶媒と、を混合した第2薬液を、前記窒化シリコン膜の前記第2主面に供給する工程、
(b−4)前記半導体基板に対して、第3熱処理を施す工程、
(b−5)前記高分子有機化合物をシンナーで除去する工程、
を有する、半導体装置の製造方法。
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