JP2016046447A - 貫通電極を含む半導体構造とその形成方法 - Google Patents

貫通電極を含む半導体構造とその形成方法 Download PDF

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JP2016046447A
JP2016046447A JP2014171019A JP2014171019A JP2016046447A JP 2016046447 A JP2016046447 A JP 2016046447A JP 2014171019 A JP2014171019 A JP 2014171019A JP 2014171019 A JP2014171019 A JP 2014171019A JP 2016046447 A JP2016046447 A JP 2016046447A
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Prior art keywords
hole
electrode portion
electrode
layer
uppermost
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JP2014171019A
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JP5959071B2 (ja
Inventor
末岡　邦昭
Kuniaki Sueoka
邦昭 末岡
晃啓 堀部
Akihiro Horibe
晃啓 堀部
和重 鳥山
Kazushige Toriyama
和重 鳥山
森　裕幸
Hiroyuki Mori
裕幸 森
靖光 折井
Yasumitsu Orii
靖光 折井
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International Business Machines Corp
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International Business Machines Corp
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Priority to JP2014171019A priority Critical patent/JP5959071B2/ja
Priority to US14/833,368 priority patent/US9466533B2/en
Priority to US14/967,640 priority patent/US9373545B2/en
Publication of JP2016046447A publication Critical patent/JP2016046447A/ja
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Abstract

【課題】工程数が少なく低コストの縦方向の電気的接続構造を提供する。【解決手段】本発明の貫通電極を含む半導体構造１００は、（ａ）少なくとも３層を含む積層体であって、各層は垂直方向で位置合わせされた電極部１６、１８、２０を備え、最上層の電極部２０は最上層の表面上にあって開口を含み、中間層の電極部１８は最上層の開口よりも小さい開口を備える積層体と、（ｂ）積層体の最上層の電極部の開口から最下層の電極部の表面に至る貫通口３２であって、貫通口内の電極部の間の側壁は凹部を有する貫通口と、（ｃ）貫通口内の電極部の表面上を除く全ての側壁上に設けられた絶縁層４０と、（ｄ）貫通口内に最下層の電極部１６の表面から最上層の電極部２０の表面まで充填された導電材料４６と、を備える。【選択図】図９

Description

本発明は、半導体構造に関し、より具体的には、貫通電極を含む積層された半導体構造と、その半導体構造中の貫通電極の形成方法に関する。
半導体の３次元集積は、これまでの２次元スケーリングによる性能向上の壁を打ち破るために重要な技術である。しかしながら、従来の集積方法においては、コストの問題があり、３次元集積は広く利用されているとはいえない状況にある。そのコストの問題の一つとして、縦方向の電気的接続のための導体形成およびその接続が高価なものとなっていることが挙げられる。今後、３次元集積の利用が拡大するためには、低コストの集積方法（プロセス）を開発する必要がある。
特許文献１と特許文献２は、いずれもシリコン貫通ビア（TSV：Through Silicon Via）を含む多層構造の半導体装置を開示する。しかし、これらの文献開示の製法では、予めＴＳＶを形成した基板（層）を接合させてＴＳＶを連結させるものであって、縦方向の電気的接続のための導体形成およびその接続が多工程になり、高価なものとなっている。
特開2011-159889号公報 特開2014-57065号公報
したがって、本発明の目的は、積層された半導体構造において、低コストの縦方向の電気的接続構造を提供することであり、より具体的には、工程数が少なく低コストの縦方向の電気的接続構造を提供することである。
本発明の一態様では、貫通電極を含む半導体構造が提供される。その半導体構造は、（ａ）少なくとも３層を含む積層体であって、各層は垂直方向で位置合わせされた電極部を備え、最上層の電極部は最上層の表面上にあって開口を含み、中間層の電極部は最上層の開口よりも小さい開口を備える積層体と、（ｂ）積層体の最上層の電極部の開口から最下層の電極部の表面に至る貫通口であって、貫通口内の電極部の間の側壁は凹部を有する貫通口と、（ｃ）貫通口内の電極部の表面上を除く全ての側壁上に設けられた絶縁層と、（ｄ）貫通口内に最下層の電極部の表面から最上層の電極部の表面まで充填された導電材料と、を備える。
本発明の一態様によれば、積層体中の垂直方向で位置合わせされた電極部における貫通口内の電極部の間の側壁は凹部を有するので、貫通口内の各電極部の表面（側壁）がその凹部よりも突出すること（overhang）になり、貫通口内に充填される導電材料と各電極部との電気的接続を確実に取ることができる。その結果、深い貫通口（貫通電極）であってもその貫通電極を介して各層（基板）間の縦方向の電気的接続性を向上させることが可能となる。
本発明の一態様では、半導体構造中の貫通電極の形成方法が提供される。その形成方法では、（ａ）積層された少なくとも３層を含む半導体構造を準備するステップであって、各層は垂直方向で位置合わせされた電極部を備え、最上層の電極部は最上層の表面上にあって開口を含み、中間層の電極部は最上層の電極部の開口よりも小さい開口を備えるステップと、（ｂ）半導体構造の最上層の電極部のみを露出させるマスクを用いて、異方性エッチングにより、最上層の電極部の開口から最下層の電極部の表面に至る貫通口を形成するステップと、（ｃ）貫通口に等方性エッチングを適用して、貫通口内の電極部の間の側壁に凹部を形成するステップと、（ｄ）凹部が形成された貫通口内の側壁上に絶縁層を形成するステップと、（ｅ）絶縁層が形成された貫通口に異方性エッチングを適用して、貫通口内の電極部の表面を露出させるステップと、（ｆ）電極部の表面が露出した貫通口に導電材料を充填するステップと、を含む。
本発明の一態様によれば、積層体中の垂直方向で位置合わせされた電極部において一工程で貫通口を形成し、その貫通口内に各電極部に電気的接続する導電材料を充填して貫通電極を形成するので、少ない工程数で縦方向の電気的接続構造を得ることができる。また、電極部を１つのハードマスクとして用いることで、貫通口の異方性エッチングのプロセスマージンが向上する。さらに、貫通口の異方性エッチング後に等方性エッチングをおこなって、電極部間の側壁（表面）をオーバーハング状（凹部状）にエッチングし、その部分に絶縁層を堆積させることで、その後の電極部の表面（側壁）露出のための異方性エッチングのプロセスマージンを向上させることができる。
本発明の方法のフローを示す図である。 本発明の方法の各工程の断面図である。 本発明の方法の各工程の断面図である。 本発明の方法の各工程の断面図である。 本発明の方法の各工程の断面図である。 本発明の方法の各工程の断面図である。 本発明の方法の各工程の断面図である。 本発明の方法の各工程の断面図である。 本発明の方法の各工程の断面図である。 図２の工程の説明図である。
図面を参照しながら本発明の実施の形態を説明する。図１は、本発明の方法のフローを示す図である。図２〜図９は、本発明の方法の各工程の断面図である。図１０は、図２の工程の説明図である。なお、以下の説明では、３つの半導体基板を積層して１つの半導体構造を形成しているが、本発明の方法が適用可能な半導体構造はこの形態に限定されず、３以上の任意の数の半導体基板あるいはこれに準ずる配線基板（回路基板）等を含むことができる。
図１のステップＳ１１において、積層された少なくとも３層を含む半導体構造を準備する。図２に示すように、半導体構造１００は、３つの半導体基板１０、１２、１４が有機材料２２、２４を介して積層されている。半導体基板の材料は、シリコン等の任意の半導体材料を含むことができる。本発明は、その半導体材料の特定の種類に限定されない。半導体基板の各々は、複数の配線層（トランジスタ等のデバイスを含む）及び絶縁層を含むことができる。
各半導体基板の表面層は、垂直方向で位置合わせされた電極部１６、１８、２０を備える。最上層の電極部２０はその表面上に開口２６を含む。中間層の電極部１８は、最上層の電極部２０の開口２６よりも小さい開口２８を含む。なお、図２では１組の電極部１６、１８、２０のみが示されているが、同様な組（構成）の電極部が他の任意の位置において複数含むことができることは言うまでもない。この点、図３〜図９においても同様である。
図１０の（ａ）は、積層前の３つの半導体基板１０、１２、１４の上面図である。図１０の（ｂ）と（ｃ）は、積層後の３つの半導体基板１０、１２、１４、すなわち半導体構造１００の上面図と断面図である。（ａ）に示されるように、半導体基板１０、１２、１４の表面層上には円形の電極部１６、１８、２０が設けられている。電極部１６はベタで導電材料を含む。電極部１８、２０は、円形の導電材料中に開口部２８、２６を含む。導電材料は、Ｃｕ、Ｎｉ等、半導体基板で利用可能な任意の金属材料を用いることができる。本発明の方法は、電極部１６、１８、２０の特定の導電材料に限定されず、基本的に任意の導電材料（金属材料）に適用可能である。
開口部２６のサイズ（内径）は、開口部２８のサイズ（内径）よりも大きい。（ｂ）に示されるように、３つの半導体基板１０、１２、１４は、電極部１６、１８、２０が垂直方向で重なるように位置合わせされた後、（ｃ）に示すように有機材料２２、２４を介して接合される。有機材料２２、２４は、例えば熱硬化性の樹脂（高分子材料）を用いることができる。その接合方法は、例えば従来の半導体ウェハの接合方法を利用することができる。本発明の方法は、特定の接合方法に限定されない。
ステップＳ１２において、半導体構造に貫通口を形成する。図３に示すように、半導体構造１００の最上層の電極部２０のみを露出させるマスク３０を用いて、異方性エッチングにより、最上層の電極部２０の開口２６から最下層の電極部１６の表面に至る貫通口３２を形成する。異方性エッチングは、例えば、誘導結合プラズマ（ＩＣＰ）エッチング、あるいはイオンビームを用いるイオンミリング等を用いて行う。なお、本発明における“貫通口（孔）”は、半導体構造１００の中で、積層された半導体基板の少なくとも２以上を貫通する意味で用いている。例えば、図３の例では、貫通口３２は半導体基板１２、１４を貫通している。
この異方性エッチングにおいて、最上の電極部２０（の開口２６）はその下側の開口部３３の内径を規定する１つのハードマスクとして機能する。同様に、中間の電極部１８（の開口２８）はその下側の開口部３４の内径を規定する１つのハードマスクとして機能する。このように、半導体構造体中の電極部が貫通口を形成するための１つのハードマスクとして機能させることに本発明の方法の１つの特徴がある。
ステップＳ１３において、貫通口内の側壁に凹部を形成する。図４に示すように、貫通口３２に等方性エッチングを適用して、貫通口内の電極部１６、１８、２０の間の側壁に凹部３６、３８を形成する。この等方性エッチングにおいても、最上の電極部２０（の開口２６）と中間の電極部１８（の開口２８）は、電極間の側壁をエッチングする際の１つのハードマスクとして機能する。凹部３６、３８の形成により、電極部２０、１８の側壁が凹部３６、３８よりも突出すること（overhang）ことになる。
ステップＳ１４において、凹部が形成された貫通口内の側壁上に絶縁層を形成する。図５に示すように、最初に図４のマスク３０を除去した後の半導体構造において、貫通口３２内の側壁（凹部）３６、３８及び各電極１６、１８、２０の側壁（表面）上と半導体基板１４の最上層の表面上に絶縁層４０を形成する。絶縁層４０は、例えば貫通口３２内の側壁３６、３８等上での表面反応を利用してコンフォーマルな有機重合層（例えばポリイミド等）を形成することにより得ることができる。絶縁層４０の材料として、低誘電率（low-k）、あるいは低ヤング率の誘電材料（有機材料）を用いることができる。これにより、最終的に出来る貫通電極の高周波数特性が改善され、あるいは貫通電極への応力を緩和させることが可能となる。
ステップＳ１５において、貫通口内の電極の表面（側壁）を露出させる。図６に示すように、最初に表面の絶縁層４０の上にマスク４２を形成した後に、貫通口３２に異方性エッチングを適用して、貫通口３２内の電極部１６、１８、２０の表面を露出させる。異方性エッチングは、上述したステップＳ１２の方法と同様な方法で行うことができる。先のステップＳ１３において電極部２０、１８の側壁を突出させた（overhang）ので（図４）、この異方性エッチングにおいて、電極部２０、１８の側壁（表面）上の絶縁層４０を優先的に（先に）エッチング（除去）することができる。すなわち、電極部間の絶縁層４０は残しながら、電極部２０、１８の側壁（表面）を確実に露出させることができる。
ステップＳ１６において、貫通口内の側壁にバリア層、或いは、シード層、さらには、貫通口内表面の濡れ性向上のための導電層を形成する。例えば、図７に示すように、貫通口３２内において、電極部１６、１８、２０の表面及び絶縁層４０を覆い、かつ表面のマスク４２を覆う導電層４４を形成する。導電層４４は、例えば従来からあるスパッタリングやグプラズマＣＶＤ等の薄膜形成技術を用いて形成することができる。導電層４４は、例えばＣｕまたはＮｉからなる。この導電層４４の形成は本発明の必須の要件ではないが、次の導電材料の充填工程を円滑に行うため、より具体的には、例えば導電材料としてハンダ材料を用いる場合にその濡れ性を確保するために行う。
ステップＳ１７において、貫通口内に導電材料を充填する。図８に示すように、最初にいわゆるリフトオフ（lift off）によりマスク４２と共に表面の導電層４４を除去する。次に、図９に示すように、貫通口３２内に導電材料４６を充填する。導電材料の充填は、例えば、インジェクション・モールド・ソルダー（ＩＭＳ）によりハンダ材料を貫通口３２内に充填することにより行うことができる。
ハンダ材料は、Ｓｎ単体、Ａｇ、Ａｕ、Ｃｕ、Ｎｉ、Ｂｉ、Ｉｎ、Ｚｎ、Ｃｏ、Ｇｅ、Ｆｅ、及びＴｉを含むグループの中から選択された少なくとも１つの金属を含有するＳｎ、またはＩｎを主成分とするＰｂフリーハンダ金属からなる。ハンダ材料以外の比較的流動性の高い他の導電材料を用いることもできる。図９の貫通口３２内の導電材料４６により、各電極部１６、１８、２０の露出した表面に電気的に接続する縦（垂直）方向の貫通電極を得ることができる。その際、電極部１６、１８、２０間の絶縁層４０の存在により、貫通口３２内の電極部以外の半導体基板の側壁との電気的短絡（ショート）を確実に防ぐことができる。
本発明の実施形態について、図を参照しながら説明をした。しかし、本発明はこれらの実施形態に限られるものではない。本発明はその趣旨を逸脱しない範囲で当業者の知識に基づき種々なる改良、修正、変形を加えた態様で実施できるものである。
１０、１２、１４ 半導体基板
１６、１８、２０ 電極部
２０、２４ 有機材料（誘電材料、樹脂）
２６、２８ ３３、３４ 開口
３０、４２ マスク
３２ 貫通口
４４ 導電層
４６ 導電材料
１００ 半導体構造

Claims (11)

  1. 貫通電極を含む半導体構造であって、
    少なくとも３層を含む積層体であって、各層は垂直方向で位置合わせされた電極部を備え、最上層の電極部は最上層の表面上にあって開口を含み、中間層の電極部は最上層の開口よりも小さい開口を備える、前記積層体と、
    前記積層体の前記最上層の電極部の前記開口から最下層の電極部の表面に至る貫通口であって、前記貫通口内の前記電極部の間の側壁は凹部を有する、前記貫通口と、
    前記貫通口内の前記電極部の表面上を除く全ての側壁上に設けられた絶縁層と、
    前記貫通口内に前記最下層の電極部の表面から前記最上層の電極部の表面まで充填された導電材料と、を備える半導体構造。
  2. 前記積層体は、有機材料を介して積層された少なくとも３つの半導体基板を含み、前記電極部の各々は、対応する半導体基板の表面に設けられている、請求項１に記載の半導体構造。
  3. 前記貫通口内において、前記電極部の表面及び前記絶縁層を覆い、前記導電材料の表面に接する導電層をさらに備える、請求項１に記載の半導体構造。
  4. 前記絶縁層は、コンフォーマルな有機重合層からなる、請求項１に記載の半導体構造。
  5. 前記導電材料は、はんだ材料からなる、請求項１に記載の半導体構造。
  6. 半導体構造中の貫通電極の形成方法であって、
    （ａ）積層された少なくとも３層を含む半導体構造を準備するステップであって、各層は垂直方向で位置合わせされた電極部を備え、最上層の電極部は最上層の表面上にあって開口を含み、中間層の電極部は最上層の電極部の開口よりも小さい開口を備える、ステップと、
    （ｂ）前記半導体構造の前記最上層の電極部のみを露出させるマスクを用いて、異方性エッチングにより、前記最上層の電極部の開口から最下層の電極部の表面に至る貫通口を形成するステップと、
    （ｃ）前記貫通口に等方性エッチングを適用して、前記貫通口内の前記電極部の間の側壁に凹部を形成するステップと、
    （ｄ）前記凹部が形成された前記貫通口内の側壁上に絶縁層を形成するステップと、
    （ｅ）前記絶縁層が形成された前記貫通口に異方性エッチングを適用して、前記貫通口内の前記電極部の表面を露出させるステップと、
    （ｆ）前記電極部の表面が露出した前記貫通口に導電材料を充填するステップと、を含む方法。
  7. 前記半導体構造を準備するステップ（ａ）は、有機材料を介して少なくとも３つの半導体基板を積層するステップを含み、前記電極部の各々は、対応する半導体基板の表面に設けられている、請求項６に記載の方法。
  8. 前記貫通口に導電材料を充填するステップ（ｆ）の前に、前記貫通口内において、前記電極部の表面及び前記絶縁層を覆う導電層を形成するステップをさらに含む、請求項６に記載の方法。
  9. 前記貫通口内の側壁上に絶縁層を形成するステップ（ｄ）は、前記貫通口内の側壁上での表面反応を利用してコンフォーマルな有機重合層を形成するステップを含む、請求項６に記載の方法。
  10. 前記貫通口に導電材料を充填するステップ（ｆ）は、インジェクション・モールド・ソルダー（ＩＭＳ）によりハンダ材料を前記貫通口に充填するステップを含む、請求項６に記載の方法。
  11. 前記貫通口を形成するステップ（ｂ）は、前記異方性エッチングにおいて、前記最上層及び前記中間層の前記開口を有する前記電極部がハードマスクとして機能して、前記最下層の電極部の表面に至る貫通口が形成されることを含む、請求項６に記載の方法。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020088292A (ja) * 2018-11-29 2020-06-04 キヤノン株式会社 半導体装置の製造方法および半導体装置
CN113272941A (zh) * 2018-12-13 2021-08-17 超极存储器股份有限公司 半导体模块及其制造方法

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107316855A (zh) * 2016-04-27 2017-11-03 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法和电子装置
CN109119401B (zh) * 2018-08-28 2019-09-17 武汉新芯集成电路制造有限公司 半导体器件及其制作方法
US10903526B2 (en) 2018-11-30 2021-01-26 International Business Machines Corporation Electron device stack structure
US11367681B2 (en) * 2019-01-24 2022-06-21 Micron Technology, Inc. Slit oxide and via formation techniques
US11139262B2 (en) * 2019-02-07 2021-10-05 Micron Technology, Inc. Use of pre-channeled materials for anisotropic conductors
US11316143B2 (en) 2019-05-07 2022-04-26 International Business Machines Corporation Stacked device structure
US12033919B2 (en) * 2021-01-08 2024-07-09 Taiwan Semiconductor Manufacturing Company, Ltd. Backside or frontside through substrate via (TSV) landing on metal

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001044357A (ja) * 1999-07-26 2001-02-16 Seiko Epson Corp 半導体装置およびその製造方法
JP2001094039A (ja) * 1999-09-21 2001-04-06 Seiko Epson Corp 絶縁膜の形成方法および半導体チップの接続方法ならびに半導体チップの製造方法、半導体装置、接続用基板、電子機器
JP2006287211A (ja) * 2005-03-08 2006-10-19 Sharp Corp 半導体装置、積層半導体装置およびそれらの製造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5876842A (en) * 1995-06-07 1999-03-02 International Business Machines Corporation Modular circuit package having vertically aligned power and signal cores
JP4608297B2 (ja) * 2004-12-06 2011-01-12 インターナショナル・ビジネス・マシーンズ・コーポレーション 積層配線基板の製造方法
US8049327B2 (en) * 2009-01-05 2011-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Through-silicon via with scalloped sidewalls
JP5426417B2 (ja) 2010-02-03 2014-02-26 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US20110207323A1 (en) * 2010-02-25 2011-08-25 Robert Ditizio Method of forming and patterning conformal insulation layer in vias and etched structures
JP2012221998A (ja) * 2011-04-04 2012-11-12 Toshiba Corp 半導体装置ならびにその製造方法
KR101932660B1 (ko) 2012-09-12 2018-12-26 삼성전자 주식회사 Ｔｓｖ 구조를 구비한 집적회로 소자 및 그 제조 방법
US20140144681A1 (en) * 2012-11-27 2014-05-29 Qualcomm Mems Technologies, Inc. Adhesive metal nitride on glass and related methods
TWI492345B (zh) * 2013-04-17 2015-07-11 Ind Tech Res Inst 半導體結構及其製作方法
KR102151177B1 (ko) * 2013-07-25 2020-09-02 삼성전자 주식회사 Ｔｓｖ 구조를 구비한 집적회로 소자 및 그 제조 방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001044357A (ja) * 1999-07-26 2001-02-16 Seiko Epson Corp 半導体装置およびその製造方法
JP2001094039A (ja) * 1999-09-21 2001-04-06 Seiko Epson Corp 絶縁膜の形成方法および半導体チップの接続方法ならびに半導体チップの製造方法、半導体装置、接続用基板、電子機器
JP2006287211A (ja) * 2005-03-08 2006-10-19 Sharp Corp 半導体装置、積層半導体装置およびそれらの製造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020088292A (ja) * 2018-11-29 2020-06-04 キヤノン株式会社 半導体装置の製造方法および半導体装置
JP7353748B2 (ja) 2018-11-29 2023-10-02 キヤノン株式会社 半導体装置の製造方法および半導体装置
CN113272941A (zh) * 2018-12-13 2021-08-17 超极存储器股份有限公司 半导体模块及其制造方法

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