JP2015533258A5 - - Google Patents

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Publication number
JP2015533258A5
JP2015533258A5 JP2015523103A JP2015523103A JP2015533258A5 JP 2015533258 A5 JP2015533258 A5 JP 2015533258A5 JP 2015523103 A JP2015523103 A JP 2015523103A JP 2015523103 A JP2015523103 A JP 2015523103A JP 2015533258 A5 JP2015533258 A5 JP 2015533258A5
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JP
Japan
Prior art keywords
bonding
patent document
wire
ball
energy
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JP2015523103A
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English (en)
Japanese (ja)
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JP6297553B2 (ja
JP2015533258A (ja
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Priority claimed from PCT/US2013/048860 external-priority patent/WO2014014643A1/en
Publication of JP2015533258A publication Critical patent/JP2015533258A/ja
Publication of JP2015533258A5 publication Critical patent/JP2015533258A5/ja
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Publication of JP6297553B2 publication Critical patent/JP6297553B2/ja
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JP2015523103A 2012-07-17 2013-07-01 ワイヤ配線構造を形成する方法 Active JP6297553B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201261672449P 2012-07-17 2012-07-17
US61/672,449 2012-07-17
PCT/US2013/048860 WO2014014643A1 (en) 2012-07-17 2013-07-01 Methods of forming wire interconnect structures

Publications (3)

Publication Number Publication Date
JP2015533258A JP2015533258A (ja) 2015-11-19
JP2015533258A5 true JP2015533258A5 (cg-RX-API-DMAC7.html) 2016-06-16
JP6297553B2 JP6297553B2 (ja) 2018-03-20

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JP2015523103A Active JP6297553B2 (ja) 2012-07-17 2013-07-01 ワイヤ配線構造を形成する方法

Country Status (6)

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US (3) US9502371B2 (cg-RX-API-DMAC7.html)
JP (1) JP6297553B2 (cg-RX-API-DMAC7.html)
KR (1) KR102094563B1 (cg-RX-API-DMAC7.html)
CN (1) CN104471693B (cg-RX-API-DMAC7.html)
TW (1) TWI531015B (cg-RX-API-DMAC7.html)
WO (1) WO2014014643A1 (cg-RX-API-DMAC7.html)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9502371B2 (en) * 2012-07-17 2016-11-22 Kulicke And Soffa Industries, Inc. Methods of forming wire interconnect structures
US9870946B2 (en) * 2013-12-31 2018-01-16 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level package structure and method of forming same
JP5686912B1 (ja) * 2014-02-20 2015-03-18 株式会社新川 バンプ形成方法、バンプ形成装置及び半導体装置の製造方法
BR112015021244A2 (en) * 2014-10-03 2018-05-08 Intel Coproration stacked stacked matrix package with vertical columns
US11145620B2 (en) 2019-03-05 2021-10-12 Asm Technology Singapore Pte Ltd Formation of bonding wire vertical interconnects
US11543362B2 (en) * 2019-05-02 2023-01-03 Asmpt Singapore Pte. Ltd. Method for measuring the heights of wire interconnections
JP2022033633A (ja) 2020-08-17 2022-03-02 キオクシア株式会社 半導体装置
KR20220045684A (ko) 2020-10-06 2022-04-13 에스케이하이닉스 주식회사 지그재그 모양의 와이어를 포함하는 반도체 패키지
KR102866415B1 (ko) 2020-11-25 2025-09-29 가부시키가이샤 신가와 반도체 장치의 제조 방법 및 반도체 장치의 제조 장치
US12057431B2 (en) * 2020-12-18 2024-08-06 Kulicke And Soffa Industries, Inc. Methods of forming wire interconnect structures and related wire bonding tools
US20240379613A1 (en) 2021-09-16 2024-11-14 Shinkawa Ltd. Pin wire forming method, wire bonding apparatus, and bonding tool
JP7741745B2 (ja) 2022-02-15 2025-09-18 キオクシア株式会社 半導体装置およびその製造方法
CN118696408A (zh) 2022-02-15 2024-09-24 库利克和索夫工业公司 确定用于产生与工件相关的多个引线弧的顺序的方法

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US5195237A (en) * 1987-05-21 1993-03-23 Cray Computer Corporation Flying leads for integrated circuits
US5172851A (en) * 1990-09-20 1992-12-22 Matsushita Electronics Corporation Method of forming a bump electrode and manufacturing a resin-encapsulated semiconductor device
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JP4744238B2 (ja) 2005-08-29 2011-08-10 田中電子工業株式会社 ワイヤの切断方法
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JP4509043B2 (ja) * 2006-02-14 2010-07-21 株式会社新川 スタッドバンプの形成方法
US8183684B2 (en) * 2007-03-23 2012-05-22 Semiconductor Components Industries, Llc Semiconductor device and method of manufacturing the same
US9502371B2 (en) * 2012-07-17 2016-11-22 Kulicke And Soffa Industries, Inc. Methods of forming wire interconnect structures

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