JP2015061258A - Ebg構造体、半導体デバイスおよび回路基板 - Google Patents
Ebg構造体、半導体デバイスおよび回路基板 Download PDFInfo
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Abstract
【解決手段】実施形態のEBG構造体は、電極面と、電極面上に設けられる第1の絶縁層と、第1の絶縁層上に設けられる第1の金属パッチと、第1の絶縁層上に、第1の金属パッチに隣接して設けられる第2の金属パッチと、第1および第2の金属パッチ上に設けられる第2の絶縁層と、第2の絶縁層上に設けられ、第1の開口部と第2の開口部を有する配線層と、配線層上に設けられる第3の絶縁層と、電極面、および、第1の金属パッチに接続され、第1の開口部を貫通する第1のビアと、電極面、および、第2の金属パッチに接続され、第2の開口部を貫通する第2のビアと、を備える。
【選択図】図1
Description
本実施形態のEBG(Electromagnetic Band Gap)構造体は、電極面と、電極面上に設けられる第1の絶縁層と、第1の絶縁層上に設けられる第1の金属パッチと、第1の絶縁層上に、第1の金属パッチに隣接して設けられる第2の金属パッチと、第1および第2の金属パッチ上に設けられる第2の絶縁層と、第2の絶縁層上に設けられ、第1の開口部と第2の開口部を有する配線層と、配線層上に設けられる第3の絶縁層と、電極面、および、第1の金属パッチに接続され、第1の開口部を貫通する第1のビアと、電極面、および、第2の金属パッチに接続され、第2の開口部を貫通する第2のビアと、を備える。
本実施形態のEBG構造体は、電極面が、複数のスリットを有すること以外は第1の実施形態と同様である。したがって、第1の実施形態と重複する内容については、記述を省略する。
本実施形態のEBG構造体は、配線層が、金属パッチに対向する幅広部を有すること以外は第1の実施形態と同様である。したがって、第1の実施形態と重複する内容については、記述を省略する。
本実施形態の回路基板は、第1ないし第3の実施形態に記載のEBG構造体を備える。第1ないし第3の実施形態と重複する内容については記述を省略する。
本実施形態の半導体デバイスは、第1ないし第3の実施形態に記載のEBG構造体を備える。第1ないし第3の実施形態と重複する内容については記述を省略する。
12 第1の絶縁層
14 第1の金属パッチ
14a 第1の空隙
14b 第1の端部
14c 第1の切り欠き
16 第2の金属パッチ
16a 第2の空隙
16b 第2の端部
16c 第2の切り欠き
22 第2の絶縁層
24 配線層
26 第3の絶縁層
34 第1のビア
36 第2のビア
44 第1の開口部
46 第2の開口部
52 スリット
54 幅広部
100 EBG構造体
200 回路基板
300 半導体デバイス
Claims (10)
- 電極面と、
前記電極面上に設けられる第1の絶縁層と、
前記第1の絶縁層上に設けられる第1の金属パッチと、
前記第1の絶縁層上に、前記第1の金属パッチに隣接して設けられる第2の金属パッチと、
前記第1および第2の金属パッチ上に設けられる第2の絶縁層と、
前記第2の絶縁層上に設けられ、第1の開口部と第2の開口部を有する配線層と、
前記配線層上に設けられる第3の絶縁層と、
前記電極面、および、前記第1の金属パッチに接続され、前記第1の開口部を貫通する第1のビアと、
前記電極面、および、前記第2の金属パッチに接続され、前記第2の開口部を貫通する第2のビアと、
を備えることを特徴とするEBG構造体。 - 前記第1の金属パッチが、第1の切り欠きまたは第1の空隙、および、櫛状の第1の端部を有し、
前記第2の金属パッチが、第2の切り欠きまたは第2の空隙、および、櫛状の第2の端部を有し、
前記第1の端部と前記第2の端部が離間してかみ合わされることを特徴とする請求項1記載のEBG構造体。 - 前記電極面が、複数のスリットを有することを特徴とする請求項1または請求項2記載のEBG構造体。
- 前記配線層が、前記第1の金属パッチ、および、前記第2の金属パッチに対向する幅広部を有することを特徴とする請求項1ないし請求項3いずれか一項記載のEBG構造体。
- 前記配線層が、前記第1の金属パッチ、および、前記第2の金属パッチの直上に設けられることを特徴とする請求項1ないし請求項4いずれか一項記載のEBG構造体。
- 前記複数のスリットが周期的に設けられることを特徴とする請求項1ないし請求項5いずれか一項記載のEBG構造体。
- 前記電極面がグラウンド面、または、電源面であることを特徴とする請求項1ないし請求項6いずれか一項記載のEBG構造体。
- 前記配線層が、前記第1の金属パッチ、および、前記第2の金属パッチの配列方向に伸長することを特徴とする請求項1ないし請求項7いずれか一項記載のEBG構造体。
- 請求項1ないし請求項8いずれか一項記載のEBG構造体を備える半導体デバイス。
- 請求項1ないし請求項8いずれか一項記載のEBG構造体を備える回路基板。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013195112A JP6168943B2 (ja) | 2013-09-20 | 2013-09-20 | Ebg構造体、半導体デバイスおよび回路基板 |
US14/460,694 US9468089B2 (en) | 2013-09-20 | 2014-08-15 | EBG structure, semiconductor device, and circuit board |
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Application Number | Priority Date | Filing Date | Title |
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JP2013195112A JP6168943B2 (ja) | 2013-09-20 | 2013-09-20 | Ebg構造体、半導体デバイスおよび回路基板 |
Publications (2)
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JP2015061258A true JP2015061258A (ja) | 2015-03-30 |
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JP2019525472A (ja) * | 2016-07-28 | 2019-09-05 | クゥアルコム・インコーポレイテッドQualcomm Incorporated | メモリモジュールの電気的結合において電子バンドギャップ(ebg)構造を提供する回路および方法 |
KR102107023B1 (ko) * | 2018-11-02 | 2020-05-07 | 삼성전기주식회사 | 안테나 장치 및 안테나 모듈 |
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Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002111304A (ja) * | 2000-09-27 | 2002-04-12 | Sharp Corp | スリット装荷型フイルタ |
JP2008277755A (ja) * | 2007-04-30 | 2008-11-13 | Samsung Electro Mech Co Ltd | 電磁気バンドギャップ構造物及び印刷回路基板 |
JP2009004791A (ja) * | 2007-06-22 | 2009-01-08 | Samsung Electro Mech Co Ltd | 電磁気バンドギャップ構造物及び印刷回路基板 |
WO2009082003A1 (ja) * | 2007-12-26 | 2009-07-02 | Nec Corporation | 電磁バンドギャップ素子及びそれを用いたアンテナ並びにフィルタ |
US20100108373A1 (en) * | 2006-11-01 | 2010-05-06 | Agency For Science, Technology And Research | Double-stacked ebg structure |
WO2011111311A1 (ja) * | 2010-03-08 | 2011-09-15 | 日本電気株式会社 | 構造体、配線基板および配線基板の製造方法 |
JP2012129271A (ja) * | 2010-12-14 | 2012-07-05 | Nec Corp | ノイズ抑制構造 |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05121913A (ja) | 1991-10-24 | 1993-05-18 | Shinko Electric Ind Co Ltd | 高周波素子用パツケージ |
JPH05144994A (ja) | 1991-11-15 | 1993-06-11 | Shinko Electric Ind Co Ltd | 高周波素子用パツケージ |
JPH05152455A (ja) | 1991-11-27 | 1993-06-18 | Shinko Electric Ind Co Ltd | 高周波素子用パツケージ |
JPH05166957A (ja) | 1991-12-13 | 1993-07-02 | Shinko Electric Ind Co Ltd | 高周波素子用パッケージ |
JPH06112352A (ja) | 1992-09-29 | 1994-04-22 | Shinko Electric Ind Co Ltd | 高周波素子用パッケージ |
JP3420913B2 (ja) | 1997-06-13 | 2003-06-30 | ミネソタ マイニング アンド マニュファクチャリング カンパニー | 半導体チップ実装用回路基板、半導体チップ収納用パッケージ、及び半導体デバイス |
JPH11163588A (ja) | 1997-12-01 | 1999-06-18 | Nippon Ceramic Co Ltd | 電磁干渉抑制体の製造方法 |
JPH11214580A (ja) | 1998-01-21 | 1999-08-06 | Kyocera Corp | 高周波素子収納用パッケージ |
JP2002124592A (ja) | 2000-10-16 | 2002-04-26 | Sharp Corp | 高周波装置 |
JP2003133462A (ja) | 2001-10-29 | 2003-05-09 | Shinko Electric Ind Co Ltd | 高周波素子用パッケージ |
JP3854570B2 (ja) | 2002-11-15 | 2006-12-06 | 新光電気工業株式会社 | 高周波素子用パッケージ |
JP4744949B2 (ja) | 2005-06-24 | 2011-08-10 | 三菱電機株式会社 | 電波遮蔽装置 |
JP5012407B2 (ja) | 2007-10-22 | 2012-08-29 | 日本電気株式会社 | Ebg材料を用いたコモンモード電流抑制フィルタ |
JP4950104B2 (ja) | 2008-03-11 | 2012-06-13 | Necトーキン株式会社 | Ebg構造体の製造方法、ebg構造体、ebg構造シート及びアンテナ装置 |
JP5135178B2 (ja) | 2008-11-25 | 2013-01-30 | 株式会社東芝 | アンテナ装置および無線通信装置 |
JP5701806B2 (ja) | 2012-03-29 | 2015-04-15 | 株式会社東芝 | Ebg構造体および半導体装置 |
JP5694251B2 (ja) | 2012-07-27 | 2015-04-01 | 株式会社東芝 | Ebg構造体および回路基板 |
-
2013
- 2013-09-20 JP JP2013195112A patent/JP6168943B2/ja not_active Expired - Fee Related
-
2014
- 2014-08-15 US US14/460,694 patent/US9468089B2/en not_active Expired - Fee Related
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002111304A (ja) * | 2000-09-27 | 2002-04-12 | Sharp Corp | スリット装荷型フイルタ |
US20100108373A1 (en) * | 2006-11-01 | 2010-05-06 | Agency For Science, Technology And Research | Double-stacked ebg structure |
JP2008277755A (ja) * | 2007-04-30 | 2008-11-13 | Samsung Electro Mech Co Ltd | 電磁気バンドギャップ構造物及び印刷回路基板 |
JP2009004791A (ja) * | 2007-06-22 | 2009-01-08 | Samsung Electro Mech Co Ltd | 電磁気バンドギャップ構造物及び印刷回路基板 |
WO2009082003A1 (ja) * | 2007-12-26 | 2009-07-02 | Nec Corporation | 電磁バンドギャップ素子及びそれを用いたアンテナ並びにフィルタ |
WO2011111311A1 (ja) * | 2010-03-08 | 2011-09-15 | 日本電気株式会社 | 構造体、配線基板および配線基板の製造方法 |
JP2012129271A (ja) * | 2010-12-14 | 2012-07-05 | Nec Corp | ノイズ抑制構造 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9848504B2 (en) | 2014-08-25 | 2017-12-19 | Kabushiki Kaisha Toshiba | Electronic device having a housing for suppression of electromagnetic noise |
JP2019525472A (ja) * | 2016-07-28 | 2019-09-05 | クゥアルコム・インコーポレイテッドQualcomm Incorporated | メモリモジュールの電気的結合において電子バンドギャップ(ebg)構造を提供する回路および方法 |
KR102107023B1 (ko) * | 2018-11-02 | 2020-05-07 | 삼성전기주식회사 | 안테나 장치 및 안테나 모듈 |
WO2023054633A1 (ja) * | 2021-09-29 | 2023-04-06 | パナソニックIpマネジメント株式会社 | 多層デバイス |
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