JP5953967B2 - 高周波モジュール - Google Patents
高周波モジュール Download PDFInfo
- Publication number
- JP5953967B2 JP5953967B2 JP2012134346A JP2012134346A JP5953967B2 JP 5953967 B2 JP5953967 B2 JP 5953967B2 JP 2012134346 A JP2012134346 A JP 2012134346A JP 2012134346 A JP2012134346 A JP 2012134346A JP 5953967 B2 JP5953967 B2 JP 5953967B2
- Authority
- JP
- Japan
- Prior art keywords
- frequency module
- connection terminal
- ground
- circuit
- resonant circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000000758 substrate Substances 0.000 claims description 18
- 239000004020 conductor Substances 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 description 30
- 230000003071 parasitic effect Effects 0.000 description 11
- 239000003990 capacitor Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 6
- 239000002184 metal Substances 0.000 description 5
- 230000000052 comparative effect Effects 0.000 description 4
- 238000004088 simulation Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Wire Bonding (AREA)
- Transceivers (AREA)
Description
10−プリント基板
10A−実装領域
11A,11B,11C,11D,11E,11F−ボンディングパッド
12A,12B−ボンディングワイヤ
12Al,12BL−寄生インダクタ成分
20−半導体チップ
21A,21B−グランド接続端子
21L,22L,23L−インダクタ
21C,22C,23C−キャパシタ
Gnd1,Gnd2−グランド用パッド
Claims (5)
- 一面の所定位置を基準とした点対称となる位置に設けられ、グランドに接続されている第1及び第2のグランド用導体パターンを有する基板と、
互いに導通する第1及び第2の接続端子を有し、前記基板の一面に実装された共振回路部と、
前記第1の接続端子と前記第1のグランド用導体パターンとを接続する第1のボンディングワイヤと、
前記第2の接続端子と前記第2のグランド用導体パターンとを接続する第2のボンディングワイヤと、
を備え、
前記共振回路部は、
前記第1の接続端子及び前記第2の接続端子を結ぶ第1の直線が、前記第1のグランド用導体パターン及び前記第2のグランド用導体パターンを結ぶ第2の直線と交差するように実装されている、
高周波モジュール。 - 前記共振回路部は、
前記第1の直線の中点が、前記所定位置に重なるように実装されている、請求項1に記載の高周波モジュール。 - 前記第1の接続端子及び前記第2の接続端子は隣接している、請求項1又は2に記載の高周波モジュール。
- 前記第1の接続端子及び前記第2の接続端子は一体形成されている、請求項1から3の何れかに記載の高周波モジュール。
- 前記共振回路部は、
信号の入力端子及び出力端子と、
前記入力端子及び前記出力端子との間に接続された並列共振回路と、
一端が前記入力端子に接続され、他端が前記第1の接続端子に接続された第1の直列共振回路と、
一端が前記出力端子に接続され、他端が前記第2の接続端子に接続された第2の直列共振回路と
を有している、
請求項1から4の何れかに記載の高周波モジュール。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012134346A JP5953967B2 (ja) | 2012-06-14 | 2012-06-14 | 高周波モジュール |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012134346A JP5953967B2 (ja) | 2012-06-14 | 2012-06-14 | 高周波モジュール |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2013258341A JP2013258341A (ja) | 2013-12-26 |
JP5953967B2 true JP5953967B2 (ja) | 2016-07-20 |
Family
ID=49954506
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012134346A Expired - Fee Related JP5953967B2 (ja) | 2012-06-14 | 2012-06-14 | 高周波モジュール |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP5953967B2 (ja) |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11204728A (ja) * | 1998-01-08 | 1999-07-30 | Toshiba Corp | 高周波半導体装置 |
JPWO2006038421A1 (ja) * | 2004-09-30 | 2008-05-15 | 三洋電機株式会社 | 電子デバイス及びこれに用いるパッケージ |
-
2012
- 2012-06-14 JP JP2012134346A patent/JP5953967B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2013258341A (ja) | 2013-12-26 |
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