JP2014507065A - シリコンウエハのシリコン貫通ビアの製造 - Google Patents
シリコンウエハのシリコン貫通ビアの製造 Download PDFInfo
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- JP2014507065A JP2014507065A JP2013546200A JP2013546200A JP2014507065A JP 2014507065 A JP2014507065 A JP 2014507065A JP 2013546200 A JP2013546200 A JP 2013546200A JP 2013546200 A JP2013546200 A JP 2013546200A JP 2014507065 A JP2014507065 A JP 2014507065A
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- silicon
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- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 150
- 239000010703 silicon Substances 0.000 title claims abstract description 149
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 144
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 235000012431 wafers Nutrition 0.000 title description 10
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- 238000000034 method Methods 0.000 claims abstract description 189
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 99
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 99
- 229910052751 metal Inorganic materials 0.000 claims abstract description 85
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 40
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 24
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 24
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 23
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- 239000010936 titanium Substances 0.000 description 3
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- AFVFQIVMOAPDHO-UHFFFAOYSA-N Methanesulfonic acid Chemical compound CS(O)(=O)=O AFVFQIVMOAPDHO-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910002808 Si–O–Si Inorganic materials 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
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- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
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- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
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- 229910001094 6061 aluminium alloy Inorganic materials 0.000 description 1
- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 description 1
- 229910017758 Cu-Si Inorganic materials 0.000 description 1
- 229910017931 Cu—Si Inorganic materials 0.000 description 1
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 1
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- JCXJVPUVTGWSNB-UHFFFAOYSA-N nitrogen dioxide Inorganic materials O=[N]=O JCXJVPUVTGWSNB-UHFFFAOYSA-N 0.000 description 1
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- ABTOQLMXBSRXSM-UHFFFAOYSA-N silicon tetrafluoride Chemical class F[Si](F)(F)F ABTOQLMXBSRXSM-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
- H01L21/02074—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a planarization of conductive layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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Abstract
【選択図】図1G
Description
1つのオプションのプロセスステップでは、窒化ケイ素パッシベーション層26が、図1Cに示すように基板18の露出した表面23に堆積される。窒化ケイ素パッシベーション層26は、シリコンプレート20がキャリア24に接合された後に基板18が反りまたは他の歪みなどの形状歪みを示す場合、応力補償層として使用される。窒化ケイ素パッシベーション層26は、基板18が後のプロセスステップで形状歪みを受けることが分かっている場合、予防的な応力補償層として使用することもできる。窒化ケイ素パッシベーション層26は、普通なら基板18の形状を反らせるか、または歪ませることになる基板18に誘起される応力に逆らうことによって基板18の形状を調整する。例えば、反った状態では、基板18は周囲エッジに沿って弓反りし、かつ部分的に内側に湾曲して、凸状または凹状形状の表面を画定することがあり、基板18の中央部分は基板18の周囲エッジよりも高いかまたは低い。反りは、プロセスのいずれかの接合もしくは加熱段階、またはシリコンプレート20の一部を除去する研削もしくは研磨ステップの間に生じることがあり、それらの段階はすべて不均一な応力をシリコンプレート20と下のキャリア24との間に生じさせることがある。窒化ケイ素パッシベーション層26はそのような形状歪みを低減させ、防湿バリアとして働くこともでき、さらに、下のフィーチャ22を環境からハーメチックシールすることができる。
1つのバージョンでは、酸化物ライナ45は、図2に示す通りおよび図1Gに示すように、シリコンプレート20の表面46、ならびにシリコンプレート20にエッチングされた貫通孔44の側壁48および底部壁49の露出した表面に堆積される。シリコンプレート20の表面46はケイ素からなることができ、またはその上にオプションの窒化ケイ素パッシベーション層26(図示のような)などの他の層を有することができる。酸化物ライナ45は、堆積チャンバ34aの堆積ゾーン30aで低温プラズマ化学気相堆積プロセスにより堆積される。このプロセスでは、テトラエチルオルトシラン(TEOS)を含むケイ素含有前駆体と、酸素ガス(O2)を含む酸素前駆体とを含む堆積ガス40aが、基板18が入っている堆積ゾーン30aに導入される。1つのバージョンでは、TEOS前駆体はヘリウムなどのキャリアガスで移送され、約400mgm(mg/分)から約12000mgm(例えば、約3000mgm)の質量流量で供給される。堆積ガス40aは、約2000から約17000sccm(例えば、約12000sccm)の流量で供給される。堆積ゾーン30aのガス圧力は、約2Torrから約8Torr(例えば、約5.5Torr)の圧力に維持される。堆積プロセスの間、基板18は、約250℃未満、例えば、約100℃から約250℃の温度に維持される。基板18は、約5mm(およそ200ミル)から約13mm(およそ500ミル)の、ガス分配器36aからの間隔に保持される。プラズマは、13.6MHzの一次周波数の電流をプロセス電極38a1、b1に約100ワットから約1200ワット(例えば、約1000ワット)の電力レベルで印加することによって維持される。その上、プラズマは、プロセス電極38a1、b1に、400kHzまでの、例えば、350kHzの二次周波数の低周波電力をさらに印加することによって増強することができる。二次電力は、約10ワットから約500ワットの電力レベルで印加することができる。結果として生じたプラズマは、約2g/cm3から約3g/cm3(例えば約2.2g/cm3)の密度を有する酸化物ライナ45を堆積させる。1つのバージョンでは、酸化物ライナ45は、約0.1ミクロンから約4ミクロン、またはさらに約4ミクロンから約6ミクロンの厚さに堆積される。
表1から、1日から10日間の暴露で酸化物ライナ材料に吸収された水蒸気の量の変化を示すデルタは、それぞれ、厚いおよび薄い酸化物ライナに対してわずか0.3%または0.4%であることが見て分かる。これは、10日の期間を通じてSi−O−Si FTIRピークに対する−OH FTIRピークの比が0.5%未満の変化であることを示している。これが意味するところは、現在の低温プロセスを使用して堆積した酸化物ライナ材料はある期間にわたって安定であり、大気から大量の水を吸収しない。対照的に、従来の酸化物堆積プロセスでは、耐湿性への耐性が少ない。酸化物は、一般に、周囲空気条件下では膜安定性が低下するので、これらの結果は驚くほどに良好であった。
低温酸化物層が、PECVDプロセスで低温でTEOSを使用して高いアスペクト比の貫通孔44に堆積される場合、結果として生じた酸化物層は、貫通孔44の高いアスペクト比に起因して下の構造への共形性が不十分であることがある。例えば、少なくとも約10のアスペクト比を有する貫通孔44は、貫通孔44の内部に非共形被覆を発生させることがある。この問題は、貫通孔44の限界寸法(CD)サイズが、さらに、小さい、例えば、約5ミクロン未満のCDである場合に悪化する。そのような高いアスペクト比で小さいCDの貫通孔44では、少なくとも約1000オングストロームの厚さをもつより厚いPECVD堆積酸化物層が、貫通孔44の底部壁49に堆積される。さらに、表面46に隣接する貫通孔44の上部のエッジおよび角部の酸化物オーバーハングが、見通し線堆積の不足に起因して後続のPVD堆積ステップ中に不十分なステップカバレッジをもたらすことがあり、貫通孔44への導体または金属材料の堆積中にボイドをもたらすこともある。これらの理由で、より共形な酸化物層が高いアスペクト比の貫通孔44にとって望ましい。共形酸化物層を熱CVDベースプロセスで堆積して、高いアスペクト比の貫通孔44の側壁48および底部壁49でさえ少なくとも約50%の共形である被覆を設けることができる。しかし、不利なことには、基板18の上面46の共形の酸化物層の酸化物厚さは、一般に、低温PECVD酸化物層の厚さよりも薄い。貫通孔44の底部壁49の共形酸化物層をエッチング除去するための後続のエッチングプロセスのエッチング速度は、孔44の底部で有効ラジカルが欠乏することに起因して上面46よりも速い。したがって、酸化物層の開口エッチングの間、上面46の共形酸化物層と低温パッシベーション窒化ケイ素層との両方がエッチング除去されるようになることがあり、望ましくない。
オプションとして、酸化物ライナ45の堆積の後、図1Hに示すように、酸化物ライナ45を密封するために、二酸化ケイ素または窒化ケイ素のシーリング層64を酸化物ライナ45の上に堆積させることができる。シーリング層64は下の酸化物ライナ45よりも高密度であり、例えば、約2g/cm3から約3g/cm3の密度を有し、酸化物ライナ45の密度よりも少なくとも約50%高い。シーリング層64は、さらに、優れた防湿バリアとして働くことが望ましい。好適なシーリング層64は、テトラエチルオルトシラン、酸素、およびヘリウム希釈物の使用などの従来のPECVDプロセスを使用して堆積される酸化ケイ素から製作することができる。このプロセスにおいて、プロセス条件は、3000mgmのTEOS、5500sccmの酸素、および6000sccmのHeのプロセスガス流を含む。チャンバは、約2Torrから約8Torr、例えば、約5.5Torrのガス圧力に維持される。堆積プロセスの間、基板18は、約100℃から約220℃、例えば、約180℃の温度に維持される。プラズマは、約200ワットから約1500ワットの電力レベルで電流をチャンバ電極に印加することによって維持される。結果として生じたプラズマは、約2g/cm3から約3g/cm3、例えば、約2.1g/cm3から約2.5g/cm3の密度を有する酸化ケイ素を含むシーリング層64を堆積させる。
研磨の後、図1Mに示すように、基板18をひっくり返して、貫通孔44の最上部の金属導体68の金属コンタクト90を露出させる。環境にさらされるときに、自然酸化膜91が、時には、TSV60の金属導体68の露出した金属コンタクト90の表面に形成されることがある。例えば、酸化銅を含む自然酸化膜99が銅などの金属導体68上に形成されることがあり、一方、酸化アルミニウムを含む自然酸化膜99がアルミニウムフィーチャ上に形成されることがある。これらの場合、図2に示す通り、自然酸化物処置プロセスを使用して自然酸化膜99を処置し、その膜を削減または除去して金属または非酸化物金属化合物を形成し、他の導体および相互接続とのより良好な電気コンタクトを可能にする。
例えば、図2の流れ図に示される窒化ケイ素および二酸化ケイ素堆積プロセスを含む様々なパッシベーションおよびライナ堆積プロセスを含む本明細書で説明するプロセスは、基板処理チャンバ100内で行うことができ、その例証の例示的な実施形態が図7に示される。本明細書で説明する堆積プロセスのいくつかまたはすべて、および自然酸化物の洗浄およびシラン浸漬などの事前堆積プロセスはこのチャンバ内で実施することができるが、しかし、エッチングプロセスは、一般に、従来のエッチングプロセスチャンバ内で実施される。チャンバ100は例示のチャンバを示すために与えられているが、しかし、当業者にとって明らかなように、他のチャンバを使用することもできる。したがって、本発明の範囲は、本明細書で説明する例示のチャンバに限定されるべきでない。一般に、チャンバ100は、基板18(シリコンウエハなどの)を処理するのに好適なプラズマ化学気相堆積(PE−CVD)チャンバである。
Claims (15)
- (a)シリコンプレートに複数の貫通孔をエッチングするステップと、前記貫通孔は側壁および底部壁を含み、
(b)前記シリコンプレートの表面ならびに前記貫通孔の前記側壁および前記底部壁に、
(i)プロセス電極およびガス分配器を含むプロセスゾーンに前記シリコンプレートを準備するステップと、
(ii)前記シリコンプレートを約250℃未満の温度に維持するステップと、
(iii)テトラエチルオルトシランを含むケイ素含有ガス、および酸素ガスを含む酸素前駆体を含む堆積ガスを前記プロセスゾーンに導入するステップと、
(iv)前記プロセス電極に第1の周波数で電流を印加することによってプラズマを形成するために前記堆積ガスにエネルギーを与えるステップと
によって酸化物ライナを堆積させるステップと、
(c)金属導体を前記貫通孔内に堆積させるステップと
を含むシリコン貫通ビア製造方法。 - ステップ(a)における前記貫通孔が少なくとも約10:1のアスペクト比を有する、請求項1に記載の方法。
- 前記シリコンプレートが約100℃から約250℃の温度に維持される、請求項1に記載の方法。
- (b)が、
(1)前記テトラエチルオルトシランを約400mg/分と約12000mg/分との間の質量流量で導入すること、または
(2)前記堆積ガスを約2000sccmと約17000sccmとの間の質量流量で導入すること
の少なくとも一方を含む、請求項1に記載の方法。 - (b)が、
(1)前記堆積ガスを約2Torrと約8Torrとの間の圧力に維持すること、ならびに
(2)前記プロセス電極に、約100ワットから約1200ワットの電力レベルでの前記第1の周波数、および400ワットまでの電力レベルでの二次周波数で電流を印加することによってプラズマを形成すること
の少なくとも一方を含む、請求項1に記載の方法。 - ステップ(b)の後で、およびステップ(c)の前に、シーリング層が前記酸化物ライナの上に堆積され、前記シーリング層が二酸化ケイ素または窒化ケイ素を含む、請求項1に記載の方法。
- ステップ(c)の後に、前記シリコンプレートの前記貫通孔内に堆積された前記金属導体の上部部分を露出させるために、前記基板をひっくり返し、前記シリコンプレートの裏面を化学機械研磨することをさらに含む、請求項1に記載の方法。
- ステップ(c)の後に、前記貫通孔内の前記金属導体の前記露出した部分に形成された自然酸化膜を、
(i)1対の還元プロセス電極を含む還元プロセスゾーンに前記シリコンプレートを準備することと、
(ii)前記シリコンプレートを約100℃から約220℃の還元温度に維持することと、
(iii)前記還元プロセスゾーン内にアンモニアまたは水素を含む還元ガスを導入することと、還元ガスの体積流量は約100sccmと約3000sccmとの間にあり、
(iv)約13.6MHzの一次周波数および約150から約1200ワットの電力レベルで前記還元プロセス電極に電力を印加することと
によって除去すること
をさらに含む、請求項1に記載の方法。 - 前記自然酸化膜の除去の後に、
(i)1対の浸漬プロセス電極を含む浸漬プロセスゾーン中に前記基板を準備することと、
(ii)前記基板を約100℃から約220℃の浸漬温度に維持することと、
(iii)約100sccmと約1000sccmとの間の体積流量のシランを含む浸漬ガスを前記プロセスゾーン内に導入することと、
(iv)約13.6MHzの一次周波数および約150と約1200ワットとの間の電力レベルで前記浸漬プロセス電極に電力を印加することと
を含むシラン浸漬ステップ
をさらに含む、請求項8に記載の方法。 - (a)シリコンプレートに複数の貫通孔をエッチングすることと、前記貫通孔は側壁および底部壁を含み、
(b)前記シリコンプレートの表面ならびに前記貫通孔の前記側壁および前記底部壁に、
(i)プロセス電極およびガス分配器を含むプロセスゾーンに前記シリコンプレートを準備することと、
(ii)テトラエチルオルトシランを含むケイ素含有ガス、および酸素ガスを含む酸素前駆体を含む堆積ガスを前記プロセスゾーン内に導入することと、
(iii)前記プロセス電極に第1の周波数で電流を印加することによってプラズマを形成するために前記堆積ガスにエネルギーを与えることと
によって酸化物ライナを堆積させることと、
(c)金属導体を前記貫通孔内に堆積させることと、
(d)プラズマを形成するために還元ガスにエネルギーを与えることによって前記貫通孔内の前記金属導体の前記露出した部分に形成された自然酸化膜を除去することと、前記還元ガスは、約100sccmと約3000sccmとの間の体積流量のアンモニアまたは水素、および約10000sccmと約20000sccmとの間の体積流量の窒素を含み、
を含むシリコン貫通ビア製造方法。 - (a)シリコンプレートに複数の貫通孔をエッチングすることと、前記貫通孔は側壁および底部壁を含み、
(b)前記シリコンプレートの表面ならびに前記貫通孔の前記側壁および前記底部壁に、
(i)プロセス電極およびガス分配器を含むプロセスゾーン内に前記シリコンプレートを準備することと、
(ii)テトラエチルオルトシランを含むケイ素含有ガス、および酸素ガスを含む酸素前駆体を含む堆積ガスを前記プロセスゾーン内に導入することと、
(iii)前記プロセス電極に第1の周波数で電流を印加することによってプラズマを形成するために前記堆積ガスにエネルギーを与えることと
によって酸化物ライナを堆積させることと、
(c)金属導体を前記貫通孔内に堆積させることと、
(d)(c)の後に、
(i)前記基板を約100℃から約220℃の温度に維持することと、
(ii)プラズマを形成するために浸漬ガスにエネルギーを与えることと、前記浸漬ガスは約100sccmと約1000sccmとの間の体積流量のシランを含み、
を含むシラン浸漬ステップを行うことと
を含むシリコン貫通ビア製造方法。 - 前記浸漬ガスが約1000から約25000sccmの流量の窒素を含む、請求項9または11に記載の方法。
- 前記シラン浸漬の後に、前記貫通孔内に堆積された前記金属導体の上に保護被覆を堆積させることをさらに含む、請求項9または11に記載の方法。
- (1)約0.5ミクロンから約6ミクロンの厚さで設けられる、酸化ケイ素または窒化ケイ素の単一層、
(2)窒化ケイ素層および酸化ケイ素層、または
(3)(i)約200Åから約1500Åの厚さの窒化ケイ素層を含む下部層、(ii)約0.5ミクロンから約3ミクロンの厚さの酸化ケイ素からなる中央層、および(iii)約0.5ミクロンから約3ミクロンの厚さの窒化ケイ素を含む上部層
のうちの少なくとも1つを含む保護被覆を堆積させることをさらに含む、請求項9または11に記載の方法。 - (a)前面、その中の1つまたは複数のフィーチャ、および裏面を有するシリコンプレートを形成することと、
(b)前記シリコンプレートを支持するためのキャリアを準備することと、
(c)前記シリコンプレートの前記裏面を露出するために、前記シリコンプレートの前記前面を前記キャリアに、それらの間の接着層を使用して接合することによって基板を形成することと、
(d)前記基板の前記シリコンプレートの前記露出した裏面に窒化ケイ素パッシベーション層を堆積させることと、
(e)前記シリコンプレート内に複数の貫通孔をエッチングすることと、前記貫通孔は側壁および底部壁を含み、
(f)複数のシリコン貫通ビアを形成するために金属導体を前記貫通孔内に堆積させることと
を含むシリコン貫通ビア製造方法。
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US12/977,060 US8329575B2 (en) | 2010-12-22 | 2010-12-22 | Fabrication of through-silicon vias on silicon wafers |
US12/977,060 | 2010-12-22 | ||
PCT/US2011/064179 WO2012087613A2 (en) | 2010-12-22 | 2011-12-09 | Fabrication of through-silicon vias on silicon wafers |
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JP2014507065A true JP2014507065A (ja) | 2014-03-20 |
JP2014507065A5 JP2014507065A5 (ja) | 2015-02-05 |
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JP2013546200A Pending JP2014507065A (ja) | 2010-12-22 | 2011-12-09 | シリコンウエハのシリコン貫通ビアの製造 |
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US (2) | US8329575B2 (ja) |
JP (1) | JP2014507065A (ja) |
KR (1) | KR20140014119A (ja) |
CN (1) | CN103348461A (ja) |
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WO (1) | WO2012087613A2 (ja) |
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US20120164827A1 (en) | 2012-06-28 |
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US8329575B2 (en) | 2012-12-11 |
US8283237B2 (en) | 2012-10-09 |
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KR20140014119A (ko) | 2014-02-05 |
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