KR100852520B1 - 전자 디바이스의 제조 방법 및 프로그램을 기록한 기록매체 - Google Patents
전자 디바이스의 제조 방법 및 프로그램을 기록한 기록매체 Download PDFInfo
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- KR100852520B1 KR100852520B1 KR1020060013737A KR20060013737A KR100852520B1 KR 100852520 B1 KR100852520 B1 KR 100852520B1 KR 1020060013737 A KR1020060013737 A KR 1020060013737A KR 20060013737 A KR20060013737 A KR 20060013737A KR 100852520 B1 KR100852520 B1 KR 100852520B1
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- insulating film
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- module
- wiring
- photoresist layer
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Images
Classifications
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B60—VEHICLES IN GENERAL
- B60C—VEHICLE TYRES; TYRE INFLATION; TYRE CHANGING; CONNECTING VALVES TO INFLATABLE ELASTIC BODIES IN GENERAL; DEVICES OR ARRANGEMENTS RELATED TO TYRES
- B60C27/00—Non-skid devices temporarily attachable to resilient tyres or resiliently-tyred wheels
- B60C27/06—Non-skid devices temporarily attachable to resilient tyres or resiliently-tyred wheels extending over the complete circumference of the tread, e.g. made of chains or cables
- B60C27/068—Non-skid devices temporarily attachable to resilient tyres or resiliently-tyred wheels extending over the complete circumference of the tread, e.g. made of chains or cables the ground-engaging part being rigid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B60—VEHICLES IN GENERAL
- B60B—VEHICLE WHEELS; CASTORS; AXLES FOR WHEELS OR CASTORS; INCREASING WHEEL ADHESION
- B60B11/00—Units comprising multiple wheels arranged side by side; Wheels having more than one rim or capable of carrying more than one tyre
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B60—VEHICLES IN GENERAL
- B60C—VEHICLE TYRES; TYRE INFLATION; TYRE CHANGING; CONNECTING VALVES TO INFLATABLE ELASTIC BODIES IN GENERAL; DEVICES OR ARRANGEMENTS RELATED TO TYRES
- B60C27/00—Non-skid devices temporarily attachable to resilient tyres or resiliently-tyred wheels
- B60C27/06—Non-skid devices temporarily attachable to resilient tyres or resiliently-tyred wheels extending over the complete circumference of the tread, e.g. made of chains or cables
- B60C27/10—Non-skid devices temporarily attachable to resilient tyres or resiliently-tyred wheels extending over the complete circumference of the tread, e.g. made of chains or cables having tensioning means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
- H01L21/02074—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a planarization of conductive layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
- H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
- H01L21/31056—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching the removal being a selective chemical etching step, e.g. selective dry etching through a mask
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Mechanical Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Cleaning Or Drying Semiconductors (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
Claims (20)
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- 반도체 기판의 표면에 성막된 제1의 절연막에 제1의 도전성 재료로 이루어지는 배선을 형성하는 단계와,상기 제1의 절연막상에, 상기 배선을 덮는 제2의 절연막을 성막하는 제2의 절연막 성막 단계와,상기 성막된 제2의 절연막상에 소정의 패턴의 포토레지스트 층을 형성하는 포토레지스트 층 형성 단계와,해당 형성된 포토레지스트 층을 이용하여 플라즈마 처리에 의해 상기 제2의 절연막에 있어서 상기 배선에 도달하는 접속 구멍을 가공 성형하는 플라즈마 가공 성형 단계와,상기 포토 레지스트 층을 제거하는 애싱 단계와,상기 제2의 절연막상에, 제2의 도전성 재료로 이루어지는 도전 막을 성막해 서 상기 접속 구멍에 상기 제2의 도전성 재료를 충전하는 접속 구멍충전 단계와,상기 성막된 도전 막을 화학 기계연마에 의해 연마하는 도전 막 연마 단계와,상기 화학 기계연마에 의해 노출한 상기 제2의 절연막을 소정의 압력하에 있어서 암모니아와 불화수소를 포함하는 혼합 기체의 분위기에 폭로하는 제2의 절연막 폭로 단계와,상기 혼합 기체의 분위기에 폭로된 상기 제2의 절연막을 소정의 온도로 가열하는 제2의 절연막 가열 단계를 갖는 것을 특징으로 하는전자 디바이스의 제조 방법.
- 제 13 항에 있어서,상기 가공 성형된 접속 구멍의 표면을 소정의 압력하에 있어서 암모니아와 불화수소를 포함하는 혼합 기체의 분위기에 폭로하는 접속 구멍표면 폭로 단계와,상기 혼합 기체의 분위기에 폭로된 접속 구멍의 표면을 소정의 온도로 가열하는 접속 구멍 표면 가열 단계를 갖는 것을 특징으로 하는전자 디바이스의 제조 방법.
- 제 14 항에 있어서,상기 소정의 온도로 가열된 접속 구멍의 표면을 도전성 배리어로 피막하는 접속 구멍 피막 단계를 더 구비하는 것을 특징으로 하는전자 디바이스의 제조 방법.
- 반도체 기판의 표면에 성막된 제1의 절연막에 제1의 도전성 재료로 이루어지는 배선을 형성하는 배선 형성 단계와,상기 제1의 절연막상에, 상기 배선을 덮는 제2의 절연막을 성막하는 제2의 절연막 성막 단계와,상기 성막된 제2의 절연막상에 소정의 패턴의 포토레지스트 층을 형성하는 포토레지스트 층 형성 단계와,해당 형성된 포토 레지스트 층을 이용하여 플라즈마 처리에 의해 상기 제2의 절연막에 있어서 상기 배선에 도달하는 접속 구멍을 가공 성형하는 플라즈마 가공 성형 단계와,상기 제2의 절연막상에, 제2의 도전성 재료로 이루어지는 도전 막을 성막하여 상기 접속 구멍에 상기 제2의 도전성 재료를 충전하는 접속 구멍충전 단계와,상기 포토 레지스트 층 및 상기 성막된 도전 막을 화학 기계연마에 의해 연마하는 도전 막 연마 단계와,상기 화학 기계연마에 의해 노출한 상기 제2의 절연막을 소정의 압력하에 있어서 암모니아와 불화수소를 포함하는 혼합 기체의 분위기에 폭로하는 제2의 절연막 폭로 단계와,상기 혼합 기체의 분위기에 폭로된 상기 제2의 절연막을 소정의 온도로 가열하는 제2의 절연막 가열 단계를 갖는 것을 특징으로 하는전자 디바이스의 제조 방법.
- 삭제
- 삭제
- 전자 디바이스의 제조 방법을 컴퓨터에 실행시키는 프로그램을 기록한 기록 매체에 있어서,반도체 기판의 표면에 성막된 제1의 절연막에 제1의 도전성 재료로 이루어지는 배선을 형성하는 배선 형성 모듈과,상기 제1의 절연막상에, 상기 배선을 덮는 제2의 절연막을 성막하는 제2의 절연막 성막 모듈과,상기 성막된 제2의 절연막상에 소정의 패턴의 포토레지스트 층을 형성하는 포토레지스트 층 형성 모듈과,해당 형성된 포토 레지스트 층을 이용하여 플라즈마 처리에 의해 상기 제2의 절연막에 있어서 상기 배선에 도달하는 접속 구멍을 가공 성형하는 플라즈마 가공 성형 모듈과,상기 포토레지스트 층을 제거하는 애싱 모듈과,상기 제2의 절연막상에, 제2의 도전성 재료로 이루어지는 도전 막을 성막 해서 상기 접속 구멍에 상기 제2의 도전성 재료를 충전하는 접속 구멍 충전 모듈과,상기 성막된 도전 막을 화학 기계연마에 의해 연마하는 도전 막 연마 모듈과,상기 화학 기계연마에 의해 노출한 상기 제2의 절연막을 소정의 압력하에 있어서 암모니아와 불화 수소를 포함하는 혼합 기체의 분위기에 폭로하는 제2의 절연막 폭로 모듈과,상기 혼합 기체의 분위기에 폭로된 상기 제2의 절연막을 소정의 온도로 가열 하는 제2의 절연막 가열 모듈을 갖는 것을 특징으로 하는프로그램을 기록한 기록 매체.
- 전자 디바이스의 제조 방법을 컴퓨터에 실행시키는 프로그램을 기록한 기록 매체에 있어서,반도체 기판의 표면에 성막된 제1의 절연막에 제1의 도전성 재료로 이루어지는 배선을 형성하는 배선 형성 모듈과,상기 제1의 절연막상에, 상기 배선을 덮는 제2의 절연막을 성막하는 제2의 절연막 성막 모듈과,상기 성막된 제2의 절연막상에 소정의 패턴의 포토레지스트 층을 형성하는 포토레지스트 층 형성 모듈과,해당 형성된 포토 레지스트 층을 이용하여 플라즈마 처리에 의해 상기 제2의 절연막에 있어서 상기 배선에 도달하는 접속 구멍을 가공 성형하는 플라즈마 가공 성형 모듈과,상기 제2의 절연막상에, 제2의 도전성 재료로 이루어지는 도전 막을 성막 해서 상기 접속 구멍에 상기 제2의 도전성 재료를 충전하는 접속 구멍충전 모듈과,상기 포토레지스트 층 및 상기 성막된 도전 막을 화학기계 연마에 의해 연마하는 도전막 연마 모듈과,상기 화학 기계연마에 의해 노출한 상기 제2의 절연막을 소정의 압력하에 있어서 암모니아와 불화수소를 포함하는 혼합 기체의 분위기에 폭로하는 제2의 절연 막 폭로 모듈과,상기 혼합 기체의 분위기에 폭로된 상기 제2의 절연막을 소정의 온도로 가열하는 제2의 절연막 가열 모듈을 갖는 것을 특징으로 하는프로그램을 기록한 기록 매체.
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JPJP-P-2005-00036717 | 2005-02-14 | ||
JP2005278841A JP4843285B2 (ja) | 2005-02-14 | 2005-09-26 | 電子デバイスの製造方法及びプログラム |
JPJP-P-2005-00278841 | 2005-09-26 |
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JP (1) | JP4843285B2 (ko) |
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KR19990088436A (ko) * | 1998-05-20 | 1999-12-27 | 가네꼬 히사시 | 구리배선을화학적기계적으로연마한후반도체웨이퍼를세정하는방법 |
US6541351B1 (en) * | 2001-11-20 | 2003-04-01 | International Business Machines Corporation | Method for limiting divot formation in post shallow trench isolation processes |
KR20050032435A (ko) * | 2003-10-01 | 2005-04-07 | 동부아남반도체 주식회사 | 반도체소자의 플러그 제조 방법 |
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JP2002110679A (ja) * | 2000-09-29 | 2002-04-12 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
JP2002299316A (ja) * | 2001-03-29 | 2002-10-11 | Toshiba Corp | プラズマ処理方法 |
JP3749860B2 (ja) * | 2001-12-04 | 2006-03-01 | 大日本スクリーン製造株式会社 | ポリマー除去方法およびポリマー除去装置 |
TWI302950B (en) * | 2002-01-28 | 2008-11-11 | Mitsubishi Chem Corp | Cleaning solution and method of cleanimg board of semiconductor device |
JP2004134783A (ja) * | 2002-09-19 | 2004-04-30 | Sumitomo Chem Co Ltd | 半導体基板用洗浄液および半導体デバイスの製造方法 |
US6656824B1 (en) * | 2002-11-08 | 2003-12-02 | International Business Machines Corporation | Low resistance T-gate MOSFET device using a damascene gate process and an innovative oxide removal etch |
US6858532B2 (en) * | 2002-12-10 | 2005-02-22 | International Business Machines Corporation | Low defect pre-emitter and pre-base oxide etch for bipolar transistors and related tooling |
US7877161B2 (en) * | 2003-03-17 | 2011-01-25 | Tokyo Electron Limited | Method and system for performing a chemical oxide removal process |
US6790733B1 (en) * | 2003-03-28 | 2004-09-14 | International Business Machines Corporation | Preserving TEOS hard mask using COR for raised source-drain including removable/disposable spacer |
US6905941B2 (en) * | 2003-06-02 | 2005-06-14 | International Business Machines Corporation | Structure and method to fabricate ultra-thin Si channel devices |
US7205228B2 (en) * | 2003-06-03 | 2007-04-17 | Applied Materials, Inc. | Selective metal encapsulation schemes |
JP4833512B2 (ja) * | 2003-06-24 | 2011-12-07 | 東京エレクトロン株式会社 | 被処理体処理装置、被処理体処理方法及び被処理体搬送方法 |
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KR19990088436A (ko) * | 1998-05-20 | 1999-12-27 | 가네꼬 히사시 | 구리배선을화학적기계적으로연마한후반도체웨이퍼를세정하는방법 |
US6541351B1 (en) * | 2001-11-20 | 2003-04-01 | International Business Machines Corporation | Method for limiting divot formation in post shallow trench isolation processes |
KR20050032435A (ko) * | 2003-10-01 | 2005-04-07 | 동부아남반도체 주식회사 | 반도체소자의 플러그 제조 방법 |
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EP1691409A1 (en) | 2006-08-16 |
TWI385722B (zh) | 2013-02-11 |
KR20060018917A (ko) | 2006-03-02 |
JP2006253633A (ja) | 2006-09-21 |
JP4843285B2 (ja) | 2011-12-21 |
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