JP2014503998A - 網目状の垂直ナノワイヤに実装された電界効果トランジスタデバイスを製造する方法、この方法で製造されるトランジスタデバイス、該トランジスタデバイスを備えた電子デバイス、および、該電子デバイスを少なくとも一つ備えた処理装置 - Google Patents
網目状の垂直ナノワイヤに実装された電界効果トランジスタデバイスを製造する方法、この方法で製造されるトランジスタデバイス、該トランジスタデバイスを備えた電子デバイス、および、該電子デバイスを少なくとも一つ備えた処理装置 Download PDFInfo
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Abstract
網目状に設けられた垂直ナノワイヤ(24)に実装された電界効果トランジスタデバイス(20)を製造する方法は、ソース電極(26)とドレイン電極(30)とを、ナノワイヤに実装された各単位トランジスタのゲート電極に対して対称的に各ナノワイヤ(24)の各端部に作るステップと、各ナノワイヤ(24)の部分を取り囲む誘電材料の層(36)のまわりに導電性材料の層(38)を堆積させることによってゲート電極を作るステップと、ここで、単一の導電層(38)は、ナノワイヤのすべてに対して使用され、導電層の厚みは、トランジスタデバイスのゲート長に対応するものであり、ナノスケールゲートを形成するために、かつゲートとソースとの間、およびゲートとドレインとの間の接触を誘電体層層(32、34)によって絶縁するステップとを備える。
Description
Claims (15)
- 複数の基本トランジスタを含み、網目状に設けられた垂直ナノワイヤに実装された電界効果トランジスタデバイスを製造する方法であって、各前記基本トランジスタは、ソース電極およびドレイン電極を含み、網目状に設けられた各前記垂直ナノワイヤの一端に置かれて、チャネルによって接続されており、各前記基本トランジスタは、各前記垂直ナノワイヤを取り囲むゲート電極を含み、前記ナノワイヤ上に実装された前記基本トランジスタの前記ドレイン、ソース、およびゲートの電極は、前記トランジスタデバイスに共通のドレイン、ソース、およびゲート電極を形成するべくそれぞれ互いに接続されており、
前記製造方法は、
各前記垂直ナノワイヤの各端部にソースおよびドレインの電極を作るステップであって、前記ソースおよびドレインの電極は、ナノワイヤ上に実装された各前記基本トランジスタの前記ゲート電極に対して対称的に配置されている、ステップと、
各ナノワイヤの部分を取り囲む誘電材料の層を堆積させることと、各ナノワイヤの前記部分を取り囲む誘電材料の各層のまわりに導電性材料の層を堆積させることと、によってゲート電極を作るステップであって、前記導電性材料の層は、網目状に設けられた前記ナノワイヤのすべてに対して共通であり、導電性材料の前記層の厚みは、前記トランジスタデバイスの前記ゲートの長さに対応する、ステップと、
ナノスケールゲートを形成して、前記ナノワイヤ上に実装された各前記基本トランジスタの前記ソースと前記ゲートとの間、および前記ドレインと前記ゲートとの間でコンタクトを形成するように、誘電材料の層を使って各電極どうしを絶縁するステップと、
を備えることを特徴とする、製造方法。 - ナノワイヤのまわりに実装された各トランジスタの前記ゲート電極に前記ソースおよびドレインの電極をセルフアライメントさせる方法を使って、前記ソースおよびドレインの電極は、前記ゲート電極に対して対称的に配置されることを特徴とする、請求項1に記載の製造方法。
- 前記誘電体を使って各ソースおよびドレインの電極を絶縁する前記ステップは、誘電材料の第1の層と誘電材料の第2の層とを堆積させることによって実行され、ゲート電極を作っている導電性材料の前記層が、誘電材料の前記第1の層の上に堆積され、誘電材料の前記第2の層が、前記ゲート電極を作っている導電性材料の前記層の上に堆積され、誘電材料の前記第1および第2の層の厚みと、前記ゲート電極を作っている導電性材料の前記層の位置とは、前記ソースおよびドレインの電極が、ナノワイヤ上に実装された各トランジスタの前記ゲート電極に対して対称的に配置されるように、あらかじめ画定されていることを特徴とする、請求項1に記載の製造方法。
- 誘電材料の前記第1の層の平坦度が、実質的に5nm以下の精度で画定されることを特徴とする、請求項3に記載の製造方法。
- 誘電材料の前記第1および第2の層の前記誘電材料は、流動性無機樹脂であることを特徴とする、請求項3または4に記載の製造方法。
- 前記ゲート電極を作っている導電性材料の前記層の厚みが、20nm未満であり、前記層の前記厚みが、前記ゲートの長さを画定することを特徴とする、請求項1から5のいずれか一項に記載の製造方法。
- 複数の基本トランジスタを含み、網目状に設けられた垂直ナノワイヤに実装されたトランジスタデバイスであって、各基本トランジスタは、ソース電極およびドレイン電極を含み、網目状に設けられた各前記垂直ナノワイヤの一端に配置されてチャネルによって接続され、各前記基本トランジスタは、網目状に設けられた各前記垂直ナノワイヤを取り囲むゲート電極を含み、前記ナノワイヤ上に実装された前記基本トランジスタの前記ドレイン、ソース、およびゲートの電極は、前記トランジスタデバイスに共通のドレイン、ソース、およびゲートの電極を形成するべくそれぞれ互いに接続されており、
前記トランジスタデバイスは、
前記ソースおよびドレインの電極が、ナノワイヤ上に実装された各前記トランジスタの前記ゲート電極に対して対称的に配置され、
トランジスタの前記ゲート電極は、各ナノワイヤの部分を取り囲む誘電材料の層と、各ナノワイヤの部分を取り囲む誘電材料の各層のまわりの導電性材料の層と、によって形成され、前記導電性材料の層は、網目状に設けられた前記ナノワイヤのすべてに対して共通であり、前記導電性材料の層の厚みは、前記トランジスタの前記ゲートの長さに対応し、
前記ナノワイヤに実装された各前記トランジスタの前記ソースとゲートとの間、および前記ドレインとゲートとの間にコンタクトを形成するべく、各ソースおよびドレインの電極を絶縁する誘電材料と
を備えることを特徴とする、トランジスタデバイス。 - 前記トランジスタの前記ゲートの長さが、20nm未満であることを特徴とする、請求項7に記載のトランジスタデバイス。
- 前記垂直ナノワイヤを取り囲んで堆積された誘電体の材料層は、アルミニウム、ジルコニウム、ハフニウム、ガドリニウム、またはランタンをベースにした酸化物、およびケイ素酸化物からなる群から選択されることを特徴とする、請求項7または8に記載のトランジスタデバイス。
- 前記垂直ナノワイヤは、元素周期表のIV族元素材料またはIII−V族元素材料から作られることを特徴とする、請求項7から9のいずれか一項に記載のトランジスタデバイス。
- 前記IV族元素材料は、シリコンであることを特徴とする、請求項10に記載のトランジスタデバイス。
- 前記導電性材料は、金属、ケイ素化合物、シリコン、および多結晶シリコンからなる群から選択されることを特徴とする、請求項7から11のいずれか一項に記載のトランジスタデバイス。
- 請求項7から12のいずれか一項に記載の網目状に設けられた垂直ナノワイヤに実装された複数のトランジスタデバイスを含む、少なくとも1つのデバイスを備えたことを特徴とする、電子デバイス。
- 前記電子デバイスは、CMOSインバータ、論理回路、マルチプレクサ、揮発性メモリ、不揮発性メモリ、およびガスまたは生化学物質を検出するデバイスからなる群から選択されることを特徴とする、請求項13に記載の電子デバイス。
- 請求項13または14に記載の少なくとも1つの電子デバイスを備える、ことを特徴とする処理装置。
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JP2015065456A (ja) * | 2014-11-14 | 2015-04-09 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | 半導体装置の製造方法、及び、半導体装置 |
JP2015159320A (ja) * | 2015-04-27 | 2015-09-03 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | 半導体装置の製造方法、及び、半導体装置 |
JP2016005005A (ja) * | 2015-08-20 | 2016-01-12 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | 半導体装置の製造方法、及び、半導体装置 |
JP2017126790A (ja) * | 2017-04-11 | 2017-07-20 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | 半導体装置 |
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WO2019130965A1 (ja) * | 2017-12-25 | 2019-07-04 | 株式会社ソシオネクスト | 出力回路 |
JPWO2019130965A1 (ja) * | 2017-12-25 | 2021-01-14 | 株式会社ソシオネクスト | 出力回路 |
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WO2019175921A1 (ja) * | 2018-03-12 | 2019-09-19 | 富士通株式会社 | 半導体装置及び半導体装置の製造方法 |
JPWO2019175921A1 (ja) * | 2018-03-12 | 2021-03-18 | 富士通株式会社 | 半導体装置及び半導体装置の製造方法 |
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JP7040598B2 (ja) | 2018-03-12 | 2022-03-23 | 富士通株式会社 | 半導体装置及び半導体装置の製造方法 |
WO2022153676A1 (ja) * | 2021-01-15 | 2022-07-21 | 国立大学法人東北大学 | 半導体デバイス、集積回路及びその製造方法 |
Also Published As
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KR20140024836A (ko) | 2014-03-03 |
US20130240983A1 (en) | 2013-09-19 |
KR101882037B1 (ko) | 2018-07-25 |
WO2012069606A2 (fr) | 2012-05-31 |
WO2012069606A3 (fr) | 2012-07-19 |
JP6035245B2 (ja) | 2016-11-30 |
EP2643848B1 (fr) | 2019-07-24 |
US9379238B2 (en) | 2016-06-28 |
FR2968125A1 (fr) | 2012-06-01 |
EP2643848A2 (fr) | 2013-10-02 |
FR2968125B1 (fr) | 2013-11-29 |
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