JP2014192521A - 電子デバイス用の接合構造及び電子デバイス - Google Patents
電子デバイス用の接合構造及び電子デバイス Download PDFInfo
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- JP2014192521A JP2014192521A JP2013069879A JP2013069879A JP2014192521A JP 2014192521 A JP2014192521 A JP 2014192521A JP 2013069879 A JP2013069879 A JP 2013069879A JP 2013069879 A JP2013069879 A JP 2013069879A JP 2014192521 A JP2014192521 A JP 2014192521A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R4/00—Electrically-conductive connections between two or more conductive members in direct contact, i.e. touching one another; Means for effecting or maintaining such contact; Electrically-conductive connections having two or more spaced connecting locations for conductors and using contact members penetrating insulation
- H01R4/02—Soldered or welded connections
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
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- H—ELECTRICITY
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
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Abstract
【解決手段】本発明に係る電子デバイス用の接合構造10の一態様は、ニッケルを含む第1金属層11と、第1金属層11の上に形成され、金、スズ及びニッケルを含む第2金属層12と、を備え、第2金属層12がAuSn共晶相を含む。
【選択図】図2
Description
図1は、本実施形態の電子デバイス100(モジュール)の断面図である。ここで断面とは、第1基板40及び第2基板60の表面に垂直な方向(基板が互いに対向する方向)における断面である。本実施形態の電子デバイス100は、第1基板40、第2基板60、チップ90、及び接合構造10を備えてよい。接合構造10は、第1基板40と第2基板60との間に位置し、第1基板40と第2基板60とを接合して、これらを電気的に接続する。また接合構造10は、第2基板60とチップ90の間に位置し、第2基板60とチップ90とを接合して、これらを電気的に接続する。なお、電子デバイス100は、接合構造10によって接合された一対の電子部品を備えてもよい。
本実施形態の接合構造10の製造方法の一例を、以下に説明する。接合構造10の製造方法は、第1基板40の表面に第1前駆体構造を形成する工程と、第2基板60の表面に第2前駆体構造を形成する工程と、第1前駆体構造と第2前駆体構造とを接合する工程と、を備える。
図3(b)は、第1基板40上に形成された第1前駆体構造21を模式的に示す断面図である。第1前駆体構造21は、第1基板40上に形成されたシード層16と、シード層16上に形成された導体層15と、導体層15上に形成され、ニッケルを主成分として含むニッケル層23と、ニッケル層23上に形成され、スズを主成分として含むスズ層24とから構成される。第1前駆体構造21は以下の方法により形成される。
図3(a)は、第2基板60上に形成された第2前駆体構造22を模式的に示す断面図である。第2前駆体構造22は、第2基板60上に設けられたシード層17と、シード層17上に形成された、金を含む金層25とから構成される。第1前駆体構造の場合と同様に、第2基板60の上にシード層17を形成し、シード層17上に金層25を形成することにより、第2前駆体構造22が形成される。金層25の形成方法としては、スパッタリング、化学気相蒸着、めっき等が挙げられる。めっきによる方法としては、無電解金めっきによる方法又は電解金めっきが挙げられる。めっき液の種類は限定されない。
第1前駆体構造21のスズ層24と第2前駆体構造22の金層25とが対向するように、第1基板40上に第2基板60を載置する。
ニッケル層23の組成、厚さ及びめっき法。
スズ層24の組成、厚さ及びめっき法。
Au層25の組成、厚さ及びめっき方法。
接合工程における加熱温度及び加熱時間。
[第1前駆体構造の形成工程]
第1基板としてシリコン基板を準備した。第1基板の寸法は10×10mmであり、第1基板の厚さは0.6mmであった。第1基板の表面(被接合部位)に、チタンからなるシード層を形成した後、電解めっきにより、銅からなる導体層をシード層上に形成した。このとき、レジストフィルムを用いたパターニングにより、導体層の寸法及び厚さを調整した。導体層の厚さは5μmであり、導体層の寸法は100×100μmであった。
第2基板としてシリコン基板を準備した。第2基板の寸法は0.2×0.2mmであり、第2基板の厚さは0.6mmであった。次に、第2基板の被接合部位に、上記の方法でシード層を形成した。電解金めっきにより金層をシード層の表面に形成した。このとき、レジストフィルムを用いたパターニングにより、金層の寸法及び厚さを調整した。金層の寸法は100×100μmであり、金層の厚さは1.7μmであった。以上の工程により、第2前駆体構造を第2基板上に形成した。
第1前駆体構造のスズ層と第2前駆体構造の金層とが対向するように、第1基板上に第2基板を載置した。この第1前駆体構造及び第2前駆体構造を窒素雰囲気において60秒間300℃に加熱することにより、両者を圧着し、急冷した。この熱圧着にはフリップチップボンダーを用いた。以上の工程により、実施例1の接合構造を作製した。
第1前駆体構造のスズ層の厚さを1.1μmとしたこと以外は実施例1と同様の方法で、実施例2の接合構造を作製した。
熱圧着において第1前駆体構造及び第2前駆体構造を320℃に加熱したこと以外は実施例2と同様の方法で、実施例3の接合構造を作製した。
第1前駆体構造のスズ層の厚さを1.6μmとしたこと以外は実施例3と同様の方法で、実施例4の接合構造を作製した。
熱圧着において第1前駆体構造及び第2前駆体構造を340℃に加熱したこと以外は実施例4と同様の方法で、実施例5の接合構造を作製した。
第2前駆体構造の金層の厚さを3.0μmとしたこと以外は実施例4と同様の方法で、実施例6の接合構造を作製した。
熱圧着において第1前駆体構造及び第2前駆体構造を340℃に加熱したこと以外は実施例6と同様の方法で、実施例7の接合構造を作製した。
実施例8の第1前駆体構造の作製過程では、レジストフィルム及びシード層を第1基板の表面から剥離する前に、ニッケル層を、リンを含まない電解ニッケルめっき液を用いて形成し、スズ層を電解スズめっきにより形成した。その後、レジストフィルム及びシード層を第1基板の表面(導体層が形成された部分を除く。)から剥離した。実施例8のニッケル層はニッケルのみからなる。ニッケル層及びスズ層の形成方法以外は実施例6と同様の方法で、実施例8の接合構造を作製した。
第1前駆体構造のニッケル層を、リンを含む電解ニッケルめっき液から形成したこと以外は実施例8と同様の方法で、実施例9の接合構造を作製した。
第1前駆体構造の導体層を電解金めっきにより形成したこと以外は実施例6と同様の方法で、実施例10の接合構造を作製した。実施例10の第1前駆体構造の導体層は、金からなる層であり、その厚さは1μmであった。
第1基板として、実施例と同じシリコン基板を用意した。第1基板の被接合部位に、チタンからなるシード層を形成した。電解銅めっきにより、銅からなる導体層をシード層の表面に形成した。このとき、レジストフィルムを用いたパターニングにより、導体層の寸法及び厚さを調整した。導体層の寸法は100×100μmであり、導体層の厚さは5μmであった。
第1基板として、実施例と同じシリコン基板を用意した。第1基板の被接合部位に、チタンからなるシード層を形成した。電解金めっきにより、金からなる導体層をシード層の表面に形成した。このとき、レジストフィルムを用いたパターニングにより、導体層の寸法及び厚さを調整した。導体層の寸法は100×100μmであり、導体層の厚さは1μmであった。
第1基板として、実施例と同じシリコン基板を用意した。第1基板の被接合部位に、チタンからなるシード層を形成した。電解金めっきにより、金からなる導体層をシード層の表面に形成した。このとき、レジストフィルムを用いたパターニングにより、導体層の寸法及び厚さを調整した。導体層の寸法は100×100μmであり、導体層の厚さは1μmであった。
各接合構造の積層方向における断面をSEMで観察した。また各断面をEDSにより分析することにより、接合構造の所定の部分における各元素の濃度を測定した。
SEMで撮影した断面の写真に基づき、実施例1〜10の接合構造10のAuSnNi合金層13とAuSn共晶層14との界面におけるクラックの有無を確認した。同様に、実施例1〜10の接合構造10のAuSn共晶層14とこれに隣接する層(残留層19又はシード層17)との界面におけるクラックの有無を確認した。下記表4に示すように、いずれの実施例の界面においても、クラックがないことが確認された。またいずれの実施例の界面においてもボイドがないことが確認された。つまり、一方、実施例1〜10の接合構造10には構造的な欠陥がないことが確認された。
各接合構造の接合強度(shear強度)を以下の方法で評価した。
A:AuSn共晶層(14)の内部が破壊された態様。
B:第1金属層11とAuSnNi合金層13との界面において接合構造が破壊された態様。
C:AuSn共晶層とAuSn共晶層に隣接する層との界面において接合構造が破壊された態様(不良モード)。
各接合構造の耐熱性を以下の方法で評価した。
Claims (8)
- ニッケルを含む第1金属層と、
前記第1金属層の上に形成され、金、スズ及びニッケルを含む第2金属層と、
を備え、
前記第2金属層がAuSn共晶相を含む、
電子デバイス用の接合構造。 - 前記第2金属層において前記第1金属層側に位置する部分に、AuSnNi合金相が存在する、
請求項1に記載の電子デバイス用の接合構造。 - 前記第2金属層において前記第1金属層の反対側に位置する部分に、前記AuSn共晶相が存在する、
請求項1又は2に記載の電子デバイス用の接合構造。 - ニッケルが前記AuSn共晶相内に偏在している、
請求項1〜3のいずれか一項に記載の電子デバイス用の接合構造。 - 前記AuSn共晶相内に偏在したニッケルの周囲にスズが偏在する、
請求項4に記載の電子デバイス用の接合構造。 - 前記第2金属層において前記第1金属層側に位置する部分が、前記AuSnNi合金相を含むAuSnNi合金層であり、
前記AuSnNi合金層内のニッケルの濃度が、前記第1金属層からの距離の増加に伴って減少する、
請求項2〜5のいずれか一項に記載の電子デバイス用の接合構造。 - 前記第1金属層内のニッケルの濃度が、前記第2金属層からの距離の減少に伴って減少する、
請求項1〜6のいずれか一項に記載の電子デバイス用の接合構造。 - 請求項1〜7のいずれか一項に記載の接合構造を備える電子デバイス。
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