JP2014063912A - 半導体装置 - Google Patents
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66977—Quantum effect devices, e.g. using quantum reflection, diffraction or interference effects, i.e. Bragg- or Aharonov-Bohm effects
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- B—PERFORMING OPERATIONS; TRANSPORTING
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- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53276—Conductive materials containing carbon, e.g. fullerenes
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- C01B32/182—Graphene
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Abstract
【解決手段】グラフェン配線構造を有する半導体装置であって、半導体素子が形成された基板10上に、配線パターンに合わせて形成された触媒下地層13と、触媒下地層13上に形成され、該触媒下地層13よりも幅の狭い触媒金属層14と、触媒金属層14の側面を成長基点とし平面方向に成長し、触媒金属層14を取り囲むように形成されたグラフェン層15と、を具備した。
【選択図】 図1
Description
図1は、第1の実施形態に係わる半導体装置の概略構造を示す断面図であり、特にグラフェン配線部分を示している。
図6は、第2の実施形態に係わる半導体装置の概略構造を示す断面図であり、特にグラフェン配線部分を示している。なお、図1と同一部分には同一符号を付して、その詳しい説明は省略する。
図7は、第3の実施形態に係わる半導体装置の概略構造を示す断面図であり、特にグラフェン配線部分を示している。なお、図1と同一部分には同一符号を付して、その詳しい説明は省略する。
なお、本発明は上述した各実施形態に限定されるものではない。
11…層間絶縁膜
12…コンタクト層
13…触媒下地層(第1の金属膜)
14…触媒金属層
15…グラフェン層
16…表面保護絶縁膜
17…配線層絶縁膜
18…コンタクト層
19…グラフェン層に添加された元素
20…グラフェン配線
23…第2の金属膜
Claims (7)
- 半導体素子が形成された基板上に、配線パターンに合わせて形成された触媒下地層と、
前記触媒下地層上に該触媒下地層よりも狭い幅に形成され、上面の幅と下面の幅が異なるテーパ形状であり、表面(111)配向を有し側面にファセットが形成された触媒金属層と、
前記触媒金属層のファセットを成長基点にして平面方向に成長し、前記触媒金属層を取り囲むようにロール状に形成されたグラフェン層と、
を具備したことを特徴とする半導体装置。 - 半導体素子が形成された基板上に、配線パターンに合わせて形成された触媒下地層と、
前記触媒下地層上に形成された、該触媒下地層よりも幅の狭い触媒金属層と、
前記触媒金属層の側面を成長基点にして平面方向に成長し、前記触媒金属層を取り囲むように形成されたグラフェン層と、
を具備したことを特徴とする半導体装置。 - 半導体素子が形成された基板上に、配線パターンに合わせて形成された第1の金属膜と、
前記第1の金属膜上に形成された、該金属膜よりも幅の狭い触媒金属層と、
前記触媒金属層上に形成された第2の金属膜と、
前記触媒金属層の側面を成長基点として成長し、前記触媒金属層及び前記第2の金属膜を取り囲むように形成されたグラフェン層と、
を具備したことを特徴とする半導体装置。 - 前記触媒金属層の側面にファセットが形成され、前記グラフェン層は、前記触媒金属層のファセットを成長起点として成長していることを特徴とする請求項2又は3に記載の半導体装置。
- 前記触媒金属層は、上面の幅と下面の幅が異なるテーパ形状であり、表面(111)配向を有することを特徴とする請求項4記載の半導体装置。
- 前記グラフェン層は、ロール状に形成されていることを特徴とする請求項2〜5の何れかに記載の半導体装置。
- 前記第2の金属膜は、前記第1の金属膜よりも幅が狭く、前記触媒金属層よりも幅が広いことを特徴とする請求項3記載の半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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JP2012208669A JP5972735B2 (ja) | 2012-09-21 | 2012-09-21 | 半導体装置 |
US13/846,850 US9117851B2 (en) | 2012-09-21 | 2013-03-18 | Semiconductor device comprising a graphene wire |
US14/803,751 US9437716B2 (en) | 2012-09-21 | 2015-07-20 | Semiconductor device comprising a graphene wire |
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JP2012208669A JP5972735B2 (ja) | 2012-09-21 | 2012-09-21 | 半導体装置 |
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JP2014063912A true JP2014063912A (ja) | 2014-04-10 |
JP5972735B2 JP5972735B2 (ja) | 2016-08-17 |
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JP (1) | JP5972735B2 (ja) |
Cited By (2)
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JP6077076B1 (ja) * | 2015-09-11 | 2017-02-08 | 株式会社東芝 | グラフェン配線構造及びグラフェン配線構造の作製方法 |
US9761530B2 (en) | 2014-09-18 | 2017-09-12 | Kabushiki Kaisha Toshiba | Graphene wiring and method for manufacturing the same |
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JP5583236B1 (ja) | 2013-03-19 | 2014-09-03 | 株式会社東芝 | グラフェン配線 |
US9431346B2 (en) * | 2013-04-30 | 2016-08-30 | GlobalFoundries, Inc. | Graphene-metal E-fuse |
JP2015050305A (ja) * | 2013-08-30 | 2015-03-16 | 株式会社東芝 | 半導体装置及びその製造方法 |
WO2015126139A1 (en) * | 2014-02-19 | 2015-08-27 | Samsung Electronics Co., Ltd. | Wiring structure and electronic device employing the same |
US10050104B2 (en) | 2014-08-20 | 2018-08-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Capacitor having a graphene structure, semiconductor device including the capacitor and method of forming the same |
JP2017050503A (ja) * | 2015-09-04 | 2017-03-09 | 株式会社東芝 | 半導体装置とその製造方法 |
US9640430B2 (en) * | 2015-09-17 | 2017-05-02 | Nxp Usa, Inc. | Semiconductor device with graphene encapsulated metal and method therefor |
JP2017168505A (ja) * | 2016-03-14 | 2017-09-21 | 株式会社東芝 | 半導体装置およびその製造方法 |
US11676880B2 (en) | 2016-11-26 | 2023-06-13 | Texas Instruments Incorporated | High thermal conductivity vias by additive processing |
US10861763B2 (en) | 2016-11-26 | 2020-12-08 | Texas Instruments Incorporated | Thermal routing trench by additive processing |
US10256188B2 (en) | 2016-11-26 | 2019-04-09 | Texas Instruments Incorporated | Interconnect via with grown graphitic material |
US10529641B2 (en) | 2016-11-26 | 2020-01-07 | Texas Instruments Incorporated | Integrated circuit nanoparticle thermal routing structure over interconnect region |
US10811334B2 (en) | 2016-11-26 | 2020-10-20 | Texas Instruments Incorporated | Integrated circuit nanoparticle thermal routing structure in interconnect region |
US11004680B2 (en) | 2016-11-26 | 2021-05-11 | Texas Instruments Incorporated | Semiconductor device package thermal conduit |
US9947660B1 (en) | 2017-04-18 | 2018-04-17 | International Business Machines Corporation | Two dimension material fin sidewall |
KR102554839B1 (ko) | 2018-08-11 | 2023-07-11 | 어플라이드 머티어리얼스, 인코포레이티드 | 그래핀 확산 장벽 |
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- 2013-03-18 US US13/846,850 patent/US9117851B2/en not_active Expired - Fee Related
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JP2013201373A (ja) * | 2012-03-26 | 2013-10-03 | Toshiba Corp | 配線及び半導体装置 |
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US9924593B2 (en) | 2015-09-11 | 2018-03-20 | Kabushiki Kaisha Toshiba | Graphene wiring structure and method for manufacturing graphene wiring structure |
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US20140084250A1 (en) | 2014-03-27 |
US9437716B2 (en) | 2016-09-06 |
US20150325524A1 (en) | 2015-11-12 |
US9117851B2 (en) | 2015-08-25 |
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