JP2014049540A - 半導体装置の製造方法および半導体装置 - Google Patents
半導体装置の製造方法および半導体装置 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 91
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 71
- 238000000137 annealing Methods 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims description 27
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 58
- 229910052710 silicon Inorganic materials 0.000 abstract description 46
- 239000010703 silicon Substances 0.000 abstract description 46
- 238000013508 migration Methods 0.000 abstract description 10
- 230000005012 migration Effects 0.000 abstract description 10
- 238000005530 etching Methods 0.000 description 15
- 238000010586 diagram Methods 0.000 description 9
- 239000007789 gas Substances 0.000 description 8
- 230000001681 protective effect Effects 0.000 description 7
- 238000006243 chemical reaction Methods 0.000 description 6
- 229910052739 hydrogen Inorganic materials 0.000 description 5
- 239000001257 hydrogen Substances 0.000 description 5
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 229910001882 dioxygen Inorganic materials 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910018503 SF6 Inorganic materials 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 1
- 229960000909 sulfur hexafluoride Drugs 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
- H01L21/30655—Plasma etching; Reactive-ion etching comprising alternated and repeated etching and passivation steps, e.g. Bosch process
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
- G01L9/00—Measuring steady of quasi-steady pressure of fluid or fluent solid material by electric or magnetic pressure-sensitive elements; Transmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means
- G01L9/0041—Transmitting or indicating the displacement of flexible diaphragms
- G01L9/0042—Constructional details associated with semiconductive diaphragm sensors, e.g. etching, or constructional details of non-semiconductive diaphragms
- G01L9/0045—Diaphragm associated with a buried cavity
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
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Abstract
【解決手段】シリコン基板1のおもて面に、上端部2aと底部2bとの間の深さにおける中間部付近2cが他の深さ部分よりも外側に膨らんだ断面形状となるように2つ以上のトレンチ2を形成する。次に、高温アニール処理によってシリコン基板1のおもて面にシリコン原子の表面マイグレーションを発生させてトレンチ2の上端部2aを塞ぐことにより、シリコン基板1の内部にトレンチ2からなる複数の空洞を形成する。さらに、高温アニールをつづけることにより、複数の空洞どうしが一体化された1つの空洞部3を形成する。トレンチ2の中間部付近2cの第2開口幅x2は、トレンチ2の上端部2aの第1開口幅x1の1.1倍〜1.5倍とする。トレンチ2のアスペクト比は8以上とする。
【選択図】図1
Description
実施の形態1にかかる半導体装置の製造方法について説明する。図1は、実施の形態1にかかるSON(Silicon On Nothing)構造を備えた半導体装置の製造途中の状態を示す説明図である。図2〜5は、実施の形態1にかかるSON構造を備えた半導体装置の製造途中の状態を模式的に示す断面図である。図1(a)には、トレンチ2の平面レイアウトを示す。図1(b)には、図1(a)の切断線A−A’における断面図を示す。図1(c)には、図1(b)につづく工程により形成された空洞部3からなるSON構造の断面構造を示す。
次に、トレンチ2の断面寸法と空洞部3の断面形状および厚さとの関係について検証した。図6は、トレンチの断面寸法と空洞部の断面形状および厚さとの関係について示す特性図である。トレンチ2の断面寸法とは、トレンチ2の上端部2aの第1開口幅x1に対するトレンチ2の中間部付近2cの第2開口幅x2の比(以下、x2/x1比とする)である。
実施の形態2にかかるSON構造を備えた半導体装置の製造方法について説明する。実施の形態2にかかるSON構造を備えた半導体装置の製造方法は、異方性エッチングと側壁保護膜形成とを交互に繰り返して形成されるトレンチの断面形状が実施の形態1と異なる以外は実施の形態1と同様の構成を有する。実施の形態2にかかるSON構造を備えた半導体装置の製造方法においては、深さ方向の少なくとも1箇所に上端部の第1開口幅よりも開口幅が広くなる部分を有する断面形状でトレンチが形成される。
2 トレンチ
2a トレンチの上端部
2b トレンチの底部
2c トレンチの中間部付近
3 空洞部
x1 トレンチの上端部の第1開口幅
x2 トレンチの中間部付近の第2開口幅
x3 隣り合うトレンチの上端部間の距離
Claims (5)
- 半導体基板の内部に空洞部を有する半導体装置の製造方法であって、
前記半導体基板のおもて面に、少なくとも1箇所が外側に膨らんだ断面形状のトレンチを2つ以上形成するトレンチ形成工程と、
アニール処理によって前記トレンチの開口部を塞ぐとともに、すべての前記トレンチを一体化させて、前記半導体基板の内部に1つの前記空洞部を形成するアニール工程と、
を含むことを特徴とする半導体装置の製造方法。 - 前記トレンチ形成工程では、上端部と底部との中間付近が外側に膨らんだ断面形状の前記トレンチを形成することを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記トレンチ形成工程では、前記トレンチの外側に膨らんだ部分の開口幅を、前記トレンチの上端部の開口幅の1.1倍〜1.5倍にすることを特徴とする請求項1または2に記載の半導体装置の製造方法。
- 前記トレンチ形成工程では、前記トレンチのアスペクト比を8以上にすることを特徴とする請求項1〜3のいずれか一つに記載の半導体装置の製造方法。
- 半導体基板内部に平板状の空洞を有するSON構造を備えた半導体装置において、前記空洞の厚さが3μm以上であることを特徴とする半導体装置。
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JP2012190089A JP6160044B2 (ja) | 2012-08-30 | 2012-08-30 | 半導体装置の製造方法 |
US13/944,301 US9147579B2 (en) | 2012-08-30 | 2013-07-17 | Method of manufacturing a semiconductor device and a semiconductor device |
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JP2012190089A JP6160044B2 (ja) | 2012-08-30 | 2012-08-30 | 半導体装置の製造方法 |
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JP2014049540A true JP2014049540A (ja) | 2014-03-17 |
JP6160044B2 JP6160044B2 (ja) | 2017-07-12 |
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Families Citing this family (5)
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US10643006B2 (en) * | 2017-06-14 | 2020-05-05 | International Business Machines Corporation | Semiconductor chip including integrated security circuit |
US10170304B1 (en) | 2017-10-25 | 2019-01-01 | Globalfoundries Inc. | Self-aligned nanotube structures |
CN112533119B (zh) * | 2019-09-18 | 2022-05-06 | 无锡华润上华科技有限公司 | Mems麦克风及其制备方法 |
CN112701128B (zh) * | 2020-12-29 | 2022-04-19 | 上海烨映微电子科技股份有限公司 | Son结构及其制备方法 |
WO2024091178A1 (en) * | 2022-10-27 | 2024-05-02 | Agency For Science, Technology And Research | Semiconductor structure and method of forming the same |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001144276A (ja) * | 1999-08-31 | 2001-05-25 | Toshiba Corp | 半導体基板およびその製造方法 |
JP2002324836A (ja) * | 2001-04-24 | 2002-11-08 | Shin Etsu Handotai Co Ltd | Son構造をもつ基板を作製する方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
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US6426254B2 (en) * | 1999-06-09 | 2002-07-30 | Infineon Technologies Ag | Method for expanding trenches by an anisotropic wet etch |
US7294536B2 (en) * | 2000-07-25 | 2007-11-13 | Stmicroelectronics S.R.L. | Process for manufacturing an SOI wafer by annealing and oxidation of buried channels |
JP2003095797A (ja) | 2001-09-26 | 2003-04-03 | Toshiba Corp | 単結晶材料の製造方法及び電子装置の製造方法 |
JP2004111766A (ja) | 2002-09-20 | 2004-04-08 | Toshiba Corp | 窒化ガリウム系半導体素子及びその製造方法 |
DE102004043356A1 (de) | 2004-09-08 | 2006-03-09 | Robert Bosch Gmbh | Sensorelement mit getrenchter Kaverne |
EP1804281B1 (en) * | 2005-12-28 | 2011-12-14 | STMicroelectronics Srl | Process for digging a deep trench in a semiconductor body and semiconductor body so obtained |
JP2011049394A (ja) * | 2009-08-27 | 2011-03-10 | Toshiba Corp | 半導体装置およびその製造方法 |
WO2011055734A1 (ja) * | 2009-11-04 | 2011-05-12 | ローム株式会社 | 圧力センサおよび圧力センサの製造方法 |
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- 2012-08-30 JP JP2012190089A patent/JP6160044B2/ja not_active Expired - Fee Related
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- 2013-07-17 US US13/944,301 patent/US9147579B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2001144276A (ja) * | 1999-08-31 | 2001-05-25 | Toshiba Corp | 半導体基板およびその製造方法 |
US7019364B1 (en) * | 1999-08-31 | 2006-03-28 | Kabushiki Kaisha Toshiba | Semiconductor substrate having pillars within a closed empty space |
JP2002324836A (ja) * | 2001-04-24 | 2002-11-08 | Shin Etsu Handotai Co Ltd | Son構造をもつ基板を作製する方法 |
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US20140061868A1 (en) | 2014-03-06 |
US9147579B2 (en) | 2015-09-29 |
JP6160044B2 (ja) | 2017-07-12 |
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