JP2014011225A - 半導体装置及び半導体装置の製造方法 - Google Patents
半導体装置及び半導体装置の製造方法 Download PDFInfo
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Abstract
【解決手段】一実施形態に係る半導体装置は、複数の第1の半導体チップと、複数の第1の半導体チップが搭載される回路基板であって、複数の第1の半導体チップと電気的に接続される第1及び第2の配線導体を有する、回路基板と、を備える。複数の第1の半導体チップは、第1及び第2の配線導体と共に、第1の並列回路を構成するように、並列接続されている。複数の第1の半導体チップに均一な電流が流れるように、複数の第1の半導体チップのオン抵抗に応じて、複数の第1の半導体チップは回路基板上に配置されている。
【選択図】図3
Description
配線導体32A,32Bに第1〜第Nのトランジスタ101〜10Nを並列接続することによって構成されるべき第1の並列回路60において、入力端61から出力端62に向かう方向において、第1〜第Nのトランジスタ101〜10Nのオン抵抗が小さくなるように、第1〜第Nのトランジスタ101〜10Nを回路基板30上に配置する。
配線導体32A,32Bに第1〜第Nのダイオード201〜20Nを並列接続することによって構成されるべき第2の並列回路70において、入力端71から出力端72に向かう方向において、第1〜第Nのダイオード201〜20Nのオン抵抗が大きくなるように、第1〜第Nのダイオード201〜20Nを回路基板30上に配置する。
配線導体32A,32Bに第1〜第Nのトランジスタ101〜10Nを並列接続することによって構成されるべき第1の並列回路60において、入力端61から出力端62に向かう方向において、第1〜第Nのトランジスタ101〜10Nのオン抵抗が大きくなるように、第1〜第Nのトランジスタ101〜10Nを回路基板30上に配置する。
配線導体32A,32Bに第1〜第Nのダイオード201〜20Nを並列接続することによって構成されるべき第2の並列回路70において、入力端71から出力端72に向かう方向において、第1〜第Nのダイオード201〜20Nのオン抵抗が小さくなるように、第1〜第Nのダイオード201〜20Nを回路基板30上に配置する。
Ra>Rbである場合、半導体装置1の等価回路である第1の並列回路60では、Rt1>Rt2>・・・>RtNとなるように第1〜第Nのトランジスタ101〜10Nが並べられている。一方、Ra<Rbである場合、第1の並列回路60では、Rt1<Rt2<・・・<RtNとなるように第1〜第Nのトランジスタ101〜10Nが並べられている。そのため、入力端61から出力端62に向けて電流が流れる場合、第1〜第Nのトランジスタ101〜10Nの各々を通して流れる電流の経路において電流に作用する抵抗の値がより等しくなる。その結果、第1〜第Nのトランジスタ101〜10Nに流れる電流の均一化が図られ得る。
図7は、第2の実施形態に係る半導体装置の構成を模式的に示す図面である。半導体装置2は、第2の電極端子部33Bが、配線導体32A〜32Cの延在方向において、第1の電極端子部33Aと同じ側に位置する点で、主に、図1に示した半導体装置1の構成と相違する。この相違点を中心にして半導体装置2について説明する。
Claims (11)
- 複数の第1の半導体チップと、
前記複数の第1の半導体チップが搭載される回路基板であって、前記複数の第1の半導体チップと電気的に接続される第1及び第2の配線導体を有する、前記回路基板と、
を備え、
前記複数の第1の半導体チップは、前記第1及び第2の配線導体と共に、第1の並列回路を構成するように、並列接続されており、
前記複数の第1の半導体チップに均一な電流が流れるように、前記複数の第1の半導体チップのオン抵抗に応じて、前記複数の第1の半導体チップは前記回路基板上に配置されている、
半導体装置。 - 前記第1の並列回路における前記複数の第1の半導体チップの配列方向において、前記第1の並列回路に対する電流の入力端と出力端は互いに反対側であり、
前記第1及び第2の配線導体の抵抗は異なっており、
前記第1及び第2の配線導体のうち前記複数の第1の半導体チップへの電流供給側の配線導体の抵抗が他方の配線導体の抵抗より大きい場合、前記第1の並列回路において、前記入力端側から前記出力端側に向けて前記複数の第1の半導体チップのオン抵抗が小さくなっており、
前記第1及び第2の配線導体のうち前記複数の第1の半導体チップへの電流供給側の配線導体の抵抗が他方の配線導体の抵抗より小さい場合、前記第1の並列回路において、前記入力端側から前記出力端側に向けて前記複数の第1の半導体チップのオン抵抗が大きくなっている、
請求項1記載の半導体装置。 - 前記第1の並列回路における前記複数の第1の半導体チップの配列方向において、前記第1の並列回路に対する電流の入力端と出力端とが同じ側であり、
前記第1の並列回路において、前記複数の半導体チップのオン抵抗は、前記配列方向において、前記入力端及び前記出力端側と反対側に向けて小さくなっている、
請求項1記載の半導体装置。 - 前記複数の第1の半導体チップを構成する半導体は、ワイドバンドギャップ半導体である、
請求項1〜3の何れか一項記載の半導体装置。 - 前記第1の半導体チップは、ダイオード又はトランジスタである、
請求項1〜4の何れか一項記載の半導体装置。 - 複数の第2の半導体チップを更に備え、
前記複数の第2の半導体チップは、前記第1及び第2の配線導体と共に、第2の並列回路を構成するように、並列接続されており、
前記複数の第2の半導体チップに均一な電流が流れるように、前記複数の第2の半導体チップのオン抵抗に応じて、前記複数の第2の半導体チップは前記回路基板上に配置されている、
請求項1〜5の何れか一項に記載の半導体装置。 - 前記第1及び第2の半導体チップのうち一方がトランジスタであり、他方がダイオードである、請求項6記載の半導体装置。
- 複数の第1の半導体チップのオン抵抗を検査する工程と、
第1の配線導体と、前記第1の配線導体と絶縁された第2の配線導体とを有する回路基板に、前記複数の第1の半導体チップを搭載する工程と、
前記複数の第1の半導体チップが、前記第1及び第2の配線導体と共に第1の並列回路を構成するように、前記複数の第1の半導体チップを、前記第1及び第2の配線導体を介して並列接続する工程と、
を備え、
前記複数の第1の半導体チップを搭載する工程では、
前記複数の第1の半導体チップに均一な電流が流れるように、前記複数の第1の半導体チップのオン抵抗に応じて、前記複数の第1の半導体チップを前記回路基板上に搭載する、
半導体装置の製造方法。 - 前記第1の並列回路は、前記第1の並列回路からの電流の出力端が前記複数の第1の半導体チップの配列方向において、前記第1の並列回路からの電流の入力端と反対側に位置する前記第1の並列回路であって、
前記第1及び第2の配線導体の抵抗は異なっており、
前記複数の第1の半導体チップを搭載する工程では、
前記第1及び第2の配線導体のうち前記複数の第1の半導体チップへの電流供給側に位置すべき配線導体の抵抗が他方の配線導体の抵抗より大きい場合、前記入力端側から前記出力端側に向けて前記複数の第1の半導体チップのオン抵抗が小さくなるように、前記複数の第1の半導体チップを前記回路基板上に搭載し、
前記第1及び第2の配線導体のうち前記複数の第1の半導体チップへの電流供給側に位置すべき配線導体の抵抗が他方の配線導体の抵抗より小さい場合、前記入力端側から前記出力端側に向けて前記複数の第1の半導体チップのオン抵抗が大きくなるように、前記複数の第1の半導体チップを前記回路基板上に搭載する、
請求項8記載の半導体装置の製造方法。 - 前記第1の並列回路は、前記第1の並列回路への電流の入力端と前記第1の並列回路からの電流の出力端とが前記複数の第1の半導体チップの配列方向において、同じ側にある並列回路であって、
前記複数の第1の半導体チップを前記回路基板に搭載する工程では、前記配列方向において、前記入力端及び前記出力端側と反対側に向けて、前記複数の第1の半導体チップのオン抵抗が小さくなるように、前記複数の第1の半導体チップを前記回路基板上に搭載する、
請求項8記載の半導体装置の製造方法。 - 複数の第2の半導体チップのオン抵抗を更に検査する工程と、
前記複数の第2の半導体チップを前記回路基板上に搭載する工程と、
前記第1及び第2の配線導体と共に第2の並列回路を構成するように、前記複数の第2の半導体チップを、前記第1及び第2の配線導体を介して並列接続する工程と、
を更に備え、
前記複数の第2の半導体チップを前記回路基板上に搭載する工程では、前記複数の第2の半導体チップに均一な電流が流れるように、前記複数の第2の半導体チップのオン抵抗に応じて、前記複数の第2の半導体チップを前記回路基板上に搭載する、
請求項8〜10の何れか一項記載の半導体装置の製造方法。
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WO2022255139A1 (ja) * | 2021-06-04 | 2022-12-08 | 富士電機株式会社 | 半導体装置 |
JP7447480B2 (ja) | 2019-12-23 | 2024-03-12 | 富士電機株式会社 | 電子回路、半導体モジュール及び半導体装置 |
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