JP2013541856A - 新規なプリント回路基板及びその製造方法 - Google Patents
新規なプリント回路基板及びその製造方法 Download PDFInfo
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- JP2013541856A JP2013541856A JP2013537614A JP2013537614A JP2013541856A JP 2013541856 A JP2013541856 A JP 2013541856A JP 2013537614 A JP2013537614 A JP 2013537614A JP 2013537614 A JP2013537614 A JP 2013537614A JP 2013541856 A JP2013541856 A JP 2013541856A
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- conductive layer
- circuit board
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 48
- 238000000926 separation method Methods 0.000 claims abstract description 47
- 238000000034 method Methods 0.000 claims abstract description 28
- 239000010410 layer Substances 0.000 claims description 185
- 230000007261 regionalization Effects 0.000 claims description 26
- 230000008569 process Effects 0.000 claims description 17
- 238000010030 laminating Methods 0.000 claims description 10
- 239000002356 single layer Substances 0.000 claims description 8
- 238000007747 plating Methods 0.000 claims description 6
- 238000003475 lamination Methods 0.000 claims description 5
- 239000012790 adhesive layer Substances 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 238000002788 crimping Methods 0.000 claims 1
- 238000013461 design Methods 0.000 abstract description 6
- 239000000463 material Substances 0.000 description 16
- 239000011347 resin Substances 0.000 description 12
- 229920005989 resin Polymers 0.000 description 12
- 238000005452 bending Methods 0.000 description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 239000003365 glass fiber Substances 0.000 description 4
- 239000000470 constituent Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 239000005011 phenolic resin Substances 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000018109 developmental process Effects 0.000 description 2
- 239000002648 laminated material Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011256 inorganic filler Substances 0.000 description 1
- 229910003475 inorganic filler Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- JEIPFZHSYJVQDO-UHFFFAOYSA-N iron(III) oxide Inorganic materials O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 239000007779 soft material Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0352—Differences between the conductors of different layers of a multilayer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Laminated Bodies (AREA)
Abstract
従来、片面プリント回路基板の構造における応用制限を克服し、両面又は非対称な構造などの種々の設計を適用し得る新規な多層プリント回路基板を提供することで、生産性及び経済性を向上することができる。
【選択図】図2
Description
図3に示されるように、分離部材310は、分離用絶縁部材320の上下面のそれぞれに互いに分離可能な第1の導電層331及び第2の導電層332が順次設けられている。なお、分離部材用の第1の導電層331は、第2の導電層を保護し、分離ステップにおいて第2の導電層から分離される機能を果たす。第2の導電層332は、積層体を構成する上部絶縁部材341及び下部絶縁部材342にそれぞれ設けられ、シード層(seed)として作用し、配線を形成する機能を果たす。
Claims (13)
- (a)分離用絶縁部材の上下面のそれぞれに、互いに分離可能な第1の導電層及び第2の導電層が順次設けられた分離部材を準備するステップ;
(b)前記分離部材の上下面のそれぞれに、第1の絶縁部材とパターン形成用の第1の導電層とを順次積層するステップ;
(c)積層された第1の導電層の一領域に第1の導電性回路パターンを形成するステップ;
(d)形成された第1の導電性回路パターンの上に、それぞれ第2の絶縁部材とパターン形成用の第2の導電層とを順次積層して圧着するステップ;
(e)前記ステップ(c)〜(d)を繰り返して導電性回路パターンがn層以上積層された積層体を形成するステップ(但し、nは1〜10の自然数である);及び
(f)前記分離部材から分離用絶縁部材と第1の導電層とを取り外して第2の導電層が設けられた積層体をそれぞれ分離するステップ;
を含むことを特徴とするプリント回路基板の製造方法。 - 前記分離部材の第2の導電層は、積層体に設けられて配線を形成し、第1の導電層は、第2の導電層と分離されることを特徴とする請求項1に記載のプリント回路基板の製造方法。
- 前記第1の導電層及び第2の導電層の厚さは、それぞれ8μm〜70μmの範囲であり、第1の導電層の厚さが、第2の導電層に比べて大きいことを特徴とする請求項1に記載のプリント回路基板の製造方法。
- 前記ステップ(e)において形成された積層体の最上下面のそれぞれに位置するパターン形成用の導電層は、単層または2層以上の多層構造であることを特徴とする請求項1に記載のプリント回路基板の製造方法。
- 前記多層構造のパターン形成用導電層が互いに分離可能な第2の導電層と第1の導電層であれば、前記ステップ(f)に進むことを特徴とする請求項4に記載のプリント回路基板の製造方法。
- 前記ステップ(f)において、分離部材を中心に上部及び下部においてそれぞれ分離された積層体の構造は、互いに同一であることを特徴とする請求項1に記載のプリント回路基板の製造方法。
- 前記ステップ(f)において分離された積層体は、上下部の面にそれぞれ第2の導電層が位置し、前記積層体の内部には、所定の形状を有する導電性回路パターンと絶縁層とがn層以上交互に積層されていることを特徴とする請求項6に記載のプリント回路基板の製造方法。
- 前記分離された各積層体の垂直方向に貫通するスルーホールを少なくとも1つ以上形成するステップをさらに含むことを特徴とする請求項7に記載のプリント回路基板の製造方法。
- 前記分離された各積層体の上下面のそれぞれに設けられる第2の導電層をメッキし、回路パターンを形成するステップをさらに含むことを特徴とする請求項8に記載のプリント回路基板の製造方法。
- 請求項1乃至9のうちのいずれか1項に記載の方法により製造されたプリント回路基板。
- 分離用絶縁部材の上下面のそれぞれに、互いに分離可能な第1の導電層と第2の導電層とが順次設けられた分離部材;
前記分離部材の上下面のそれぞれに順次積層される積層用絶縁部材;及び
前記絶縁部材の上下面のぞれぞれに順次積層される導電層;
を含むプリント回路基板形成用積層体。 - 前記第1の導電層と第2の導電層とは、これらの層間に粘着層が設けられ、0.02kgf/cm以上の力が加えられると、第1の導電層と第2の導電層とが分離されることを特徴とする請求項11に記載のプリント回路基板形成用積層体。
- 請求項11に記載のプリント回路基板形成用積層体を含むプリント回路基板。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2010-0110024 | 2010-11-05 | ||
KR1020100110024A KR101282965B1 (ko) | 2010-11-05 | 2010-11-05 | 신규 인쇄회로기판 및 이의 제조방법 |
PCT/KR2011/008369 WO2012060657A2 (ko) | 2010-11-05 | 2011-11-04 | 신규 인쇄회로기판 및 이의 제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2013541856A true JP2013541856A (ja) | 2013-11-14 |
JP5955331B2 JP5955331B2 (ja) | 2016-07-20 |
Family
ID=46024971
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013537614A Active JP5955331B2 (ja) | 2010-11-05 | 2011-11-04 | 新規なプリント回路基板及びその製造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US20130299227A1 (ja) |
JP (1) | JP5955331B2 (ja) |
KR (1) | KR101282965B1 (ja) |
WO (1) | WO2012060657A2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014150250A (ja) * | 2013-01-09 | 2014-08-21 | Hitachi Chemical Co Ltd | 配線基板の製造方法及び支持材付き積層体 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
ITMI20120194A1 (it) * | 2012-02-13 | 2013-08-14 | Cedal Equipment Srl | Miglioramenti nella fabbricazione di pile di laminati plastici multistrato per circuiti stampati |
KR101514539B1 (ko) | 2013-08-29 | 2015-04-22 | 삼성전기주식회사 | 전자부품 내장기판 |
KR101932326B1 (ko) * | 2016-12-20 | 2018-12-24 | 주식회사 두산 | 인쇄회로기판 및 이의 제조방법 |
US11062985B2 (en) * | 2019-08-01 | 2021-07-13 | Advanced Semiconductor Engineering, Inc. | Wiring structure having an intermediate layer between an upper conductive structure and conductive structure |
CN111629536B (zh) * | 2020-05-22 | 2023-10-27 | 东莞联桥电子有限公司 | 一种偶数多层电路板的压合制作方法 |
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JP2005353659A (ja) * | 2004-06-08 | 2005-12-22 | Hitachi Chem Co Ltd | 多層プリント配線板の製造方法 |
JP2006039231A (ja) * | 2004-07-27 | 2006-02-09 | Matsushita Electric Works Ltd | 光電気配線混載基板の製造方法 |
JP2007158174A (ja) * | 2005-12-07 | 2007-06-21 | Shinko Electric Ind Co Ltd | 配線基板の製造方法及び電子部品実装構造体の製造方法 |
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KR100332304B1 (ko) * | 1999-05-31 | 2002-04-12 | 정해원 | 다층 인쇄회로기판 제조방법 |
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JP5092662B2 (ja) * | 2007-10-03 | 2012-12-05 | 凸版印刷株式会社 | 印刷配線板の製造方法 |
KR101025520B1 (ko) * | 2008-11-26 | 2011-04-04 | 삼성전기주식회사 | 다층 인쇄회로기판 제조방법 |
-
2010
- 2010-11-05 KR KR1020100110024A patent/KR101282965B1/ko active IP Right Grant
-
2011
- 2011-11-04 WO PCT/KR2011/008369 patent/WO2012060657A2/ko active Application Filing
- 2011-11-04 US US13/883,424 patent/US20130299227A1/en not_active Abandoned
- 2011-11-04 JP JP2013537614A patent/JP5955331B2/ja active Active
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JP2005353659A (ja) * | 2004-06-08 | 2005-12-22 | Hitachi Chem Co Ltd | 多層プリント配線板の製造方法 |
JP2006039231A (ja) * | 2004-07-27 | 2006-02-09 | Matsushita Electric Works Ltd | 光電気配線混載基板の製造方法 |
JP2007158174A (ja) * | 2005-12-07 | 2007-06-21 | Shinko Electric Ind Co Ltd | 配線基板の製造方法及び電子部品実装構造体の製造方法 |
JP2007165810A (ja) * | 2005-12-16 | 2007-06-28 | Ibiden Co Ltd | 多層プリント配線板およびその製造方法 |
JP2009032918A (ja) * | 2007-07-27 | 2009-02-12 | Shinko Electric Ind Co Ltd | 配線基板及びその製造方法と電子部品装置及びその製造方法 |
JP2007300147A (ja) * | 2007-08-21 | 2007-11-15 | Shinko Electric Ind Co Ltd | 配線基板の製造方法及び電子部品実装構造体の製造方法 |
JP2010098086A (ja) * | 2008-10-16 | 2010-04-30 | Shinko Electric Ind Co Ltd | 配線基板の製造方法 |
JP4473935B1 (ja) * | 2009-07-06 | 2010-06-02 | 新光電気工業株式会社 | 多層配線基板 |
JP2011014847A (ja) * | 2009-07-06 | 2011-01-20 | Shinko Electric Ind Co Ltd | 多層配線基板 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2014150250A (ja) * | 2013-01-09 | 2014-08-21 | Hitachi Chemical Co Ltd | 配線基板の製造方法及び支持材付き積層体 |
Also Published As
Publication number | Publication date |
---|---|
KR20120048409A (ko) | 2012-05-15 |
US20130299227A1 (en) | 2013-11-14 |
KR101282965B1 (ko) | 2013-07-08 |
WO2012060657A3 (ko) | 2012-09-07 |
JP5955331B2 (ja) | 2016-07-20 |
WO2012060657A2 (ko) | 2012-05-10 |
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