JP2013531891A5 - - Google Patents

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Publication number
JP2013531891A5
JP2013531891A5 JP2013514502A JP2013514502A JP2013531891A5 JP 2013531891 A5 JP2013531891 A5 JP 2013531891A5 JP 2013514502 A JP2013514502 A JP 2013514502A JP 2013514502 A JP2013514502 A JP 2013514502A JP 2013531891 A5 JP2013531891 A5 JP 2013531891A5
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JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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JP2013514502A
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JP2013531891A (ja
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Priority claimed from PCT/CA2011/000486 external-priority patent/WO2011156887A1/en
Publication of JP2013531891A publication Critical patent/JP2013531891A/ja
Publication of JP2013531891A5 publication Critical patent/JP2013531891A5/ja
Pending legal-status Critical Current

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JP2013514502A 2010-06-17 2011-04-26 シリコン貫通孔を有する半導体デバイス Pending JP2013531891A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US35586110P 2010-06-17 2010-06-17
US61/355,861 2010-06-17
US36244810P 2010-07-08 2010-07-08
US61/362,448 2010-07-08
PCT/CA2011/000486 WO2011156887A1 (en) 2010-06-17 2011-04-26 Semiconductor device with through-silicon vias

Publications (2)

Publication Number Publication Date
JP2013531891A JP2013531891A (ja) 2013-08-08
JP2013531891A5 true JP2013531891A5 (ja) 2014-03-13

Family

ID=45327943

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013514502A Pending JP2013531891A (ja) 2010-06-17 2011-04-26 シリコン貫通孔を有する半導体デバイス

Country Status (6)

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US (2) US9030024B2 (ja)
EP (2) EP2583303A1 (ja)
JP (1) JP2013531891A (ja)
KR (1) KR20130133748A (ja)
TW (1) TW201227883A (ja)
WO (1) WO2011156887A1 (ja)

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US9030024B2 (en) * 2010-06-17 2015-05-12 Conversant Intellectual Property Management Inc. Semiconductor device with through-silicon vias
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US8916910B2 (en) * 2010-12-13 2014-12-23 Research Foundation Of State University Of New York Reconfigurable RF/digital hybrid 3D interconnect
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US8890607B2 (en) * 2013-03-15 2014-11-18 IPEnval Consultant Inc. Stacked chip system
TW201525494A (zh) * 2013-12-26 2015-07-01 Nat Univ Tsing Hua 測試兼具容錯矽穿通道裝置
KR101503737B1 (ko) 2014-07-15 2015-03-20 연세대학교 산학협력단 반도체 장치
TWI786440B (zh) * 2015-01-13 2022-12-11 日商迪睿合股份有限公司 多層基板、及多層基板之製造方法
US9401312B1 (en) * 2015-06-11 2016-07-26 Globalfoundries Inc. TSV redundancy scheme and architecture using decoder/encoder
JP6515724B2 (ja) 2015-07-31 2019-05-22 富士通株式会社 半導体装置
KR20170030307A (ko) * 2015-09-09 2017-03-17 삼성전자주식회사 분리 배치된 커패시터를 갖는 메모리 장치
KR101737264B1 (ko) 2016-02-05 2017-05-17 연세대학교 산학협력단 3차원 집적회로
JP6822468B2 (ja) * 2016-03-24 2021-01-27 株式会社ニコン 撮像素子および撮像装置
CN107305861B (zh) * 2016-04-25 2019-09-03 晟碟信息科技（上海）有限公司 半导体装置及其制造方法
KR102395446B1 (ko) 2017-09-28 2022-05-10 삼성전자주식회사 적층형 반도체 장치, 이를 포함하는 시스템 및 적층형 반도체 장치에서의 신호 전송 방법
KR102018772B1 (ko) * 2017-12-13 2019-09-05 연세대학교 산학협력단 회전 가능한 입체도형에 기반한 예비 실리콘 관통전극을 갖는 3차원 집적회로
CN110662411B (zh) * 2019-09-12 2021-01-05 西北核技术研究院 一种具有绝缘性能自恢复的电力电气设备及其使用方法
US11837527B2 (en) * 2020-07-23 2023-12-05 Advanced Micro Devices, Inc. Semiconductor chip stack with locking through vias
US11705429B2 (en) * 2020-09-04 2023-07-18 Micron Technology, Inc. Redundant through-silicon vias
CN113113753B (zh) * 2021-03-19 2022-04-15 西安理工大学 一种基于硅通孔技术的定向耦合器

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JP4063796B2 (ja) 2004-06-30 2008-03-19 日本電気株式会社 積層型半導体装置
JP4349232B2 (ja) 2004-07-30 2009-10-21 ソニー株式会社 半導体モジュール及びｍｏｓ型固体撮像装置
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US9111588B2 (en) * 2010-12-14 2015-08-18 Rambus Inc. Multi-die DRAM banks arrangement and wiring
JP2013083619A (ja) * 2011-09-27 2013-05-09 Elpida Memory Inc 半導体チップ、半導体装置、及びその測定方法
JP2013101728A (ja) * 2011-11-07 2013-05-23 Elpida Memory Inc 半導体装置
JP2013131533A (ja) * 2011-12-20 2013-07-04 Elpida Memory Inc 半導体装置
JP5802631B2 (ja) * 2012-09-06 2015-10-28 株式会社東芝 半導体装置

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