JP2013524534A - 低コストの貫通ビアのための選択的パターニング - Google Patents
低コストの貫通ビアのための選択的パターニング Download PDFInfo
- Publication number
- JP2013524534A JP2013524534A JP2013503836A JP2013503836A JP2013524534A JP 2013524534 A JP2013524534 A JP 2013524534A JP 2013503836 A JP2013503836 A JP 2013503836A JP 2013503836 A JP2013503836 A JP 2013503836A JP 2013524534 A JP2013524534 A JP 2013524534A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- opening
- block layer
- creating
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000059 patterning Methods 0.000 title description 2
- 239000000758 substrate Substances 0.000 claims abstract description 81
- 238000000034 method Methods 0.000 claims abstract description 49
- 229910052751 metal Inorganic materials 0.000 claims abstract description 21
- 239000002184 metal Substances 0.000 claims abstract description 21
- 239000011521 glass Substances 0.000 claims abstract description 19
- 230000000903 blocking effect Effects 0.000 claims abstract description 5
- 238000001039 wet etching Methods 0.000 claims abstract description 4
- 238000000151 deposition Methods 0.000 claims description 17
- 239000004020 conductor Substances 0.000 claims description 14
- 238000004891 communication Methods 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 5
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 230000002265 prevention Effects 0.000 claims description 2
- 230000000149 penetrating effect Effects 0.000 claims 2
- 239000011810 insulating material Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 25
- 238000005530 etching Methods 0.000 abstract description 23
- 230000008021 deposition Effects 0.000 abstract description 2
- 238000003860 storage Methods 0.000 description 11
- 238000013461 design Methods 0.000 description 10
- 230000015654 memory Effects 0.000 description 10
- 239000000463 material Substances 0.000 description 8
- 230000006870 function Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 239000000203 mixture Substances 0.000 description 3
- 230000035515 penetration Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005553 drilling Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- KLDZYURQCUYZBL-UHFFFAOYSA-N 2-[3-[(2-hydroxyphenyl)methylideneamino]propyliminomethyl]phenol Chemical compound OC1=CC=CC=C1C=NCCCN=CC1=CC=CC=C1O KLDZYURQCUYZBL-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000004590 computer program Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 201000001098 delayed sleep phase syndrome Diseases 0.000 description 1
- 208000033921 delayed sleep phase type circadian rhythm sleep disease Diseases 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 230000007787 long-term memory Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 230000006403 short-term memory Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/002—Etching of the substrate by chemical or physical means by liquid chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/15—Ceramic or glass substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0388—Other aspects of conductors
- H05K2201/0394—Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/386—Improvement of the adhesion between the insulating substrate and the metal by the use of an organic polymeric bonding layer, e.g. adhesive
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
304 ブロック層
306 貫通ビア
308 第1の導電層
310 第2の導電層
312 開口部
314 絶縁層
Claims (20)
- 基板の第1の側にブロック層のパターンを作るステップと、
前記ブロック層の中に開口部を露出させるステップと、
前記ブロック層の上に第1の導電材料を堆積させるステップと、
前記第1の側と反対側の、前記基板の第2の側に貫通ビアを作るステップと、
前記貫通ビアに第2の導電材料を堆積させて、前記開口部を貫通する前記第1の導電材料に接触させるステップと
を含む、貫通ビアを製造する方法。 - 前記第2の導電材料を堆積させる前に、前記貫通ビアに絶縁材料を堆積させるステップをさらに含む、請求項1に記載の方法。
- 前記ブロック層のパターンを作るステップが、前記貫通ビアの位置に対応する前記開口部のパターンを作るステップを含む、請求項1に記載の方法。
- 前記貫通ビアを作るステップが、前記貫通ビアを形成するために前記基板をウェットエッチングするステップを含む、請求項1に記載の方法。
- 前記ブロック層のパターンを作るステップが、窒化ケイ素および炭化ケイ素の少なくとも一方のパターンを作るステップを含む、請求項1に記載の方法。
- 前記貫通ビアを作るステップが、ガラス貫通ビアを作るステップを含む、請求項1に記載の方法。
- 前記貫通ビアを集積回路に組み込むステップをさらに含む、請求項1に記載の方法。
- 前記集積回路を、モバイルフォン、セットトップボックス、音楽プレーヤ、ビデオプレーヤ、エンターテインメントユニット、ナビゲーションデバイス、コンピュータ、ハンドヘルドパーソナル通信システム(PCS)ユニット、ポータブルデータユニット、および、固定ロケーションデータユニットのうちの少なくとも1つに組み込むステップをさらに含む、請求項7に記載の方法。
- 基板と、
前記基板の第1の側における、開口部を有するブロック層と、
前記基板を貫通して延びている、前記基板の第2の側における貫通ビアと、
前記開口部の中に延びている、前記ブロック層の上の第1の導電層と、
前記ブロック層の中の開口部を貫通している前記第1の導電層と結合している、前記貫通ビアの上の第2の導電層と
を含む、集積回路。 - 前記貫通ビアの位置が、前記ブロック層の中の開口部に対応している、請求項9に記載の集積回路。
- 前記ブロック層が、窒化ケイ素および炭化ケイ素の少なくとも1つである、請求項9に記載の集積回路。
- 前記基板がガラスである、請求項9に記載の集積回路。
- モバイルフォン、セットトップボックス、音楽プレーヤ、ビデオプレーヤ、エンターテインメントユニット、ナビゲーションデバイス、コンピュータ、ハンドヘルドパーソナル通信システム(PCS)ユニット、ポータブルデータユニット、および、固定ロケーションデータユニットのうちの少なくとも1つに組み込まれている、請求項9に記載の集積回路。
- 開口部を形成するために、基板の第1の側にブロック層のパターンを作るステップと、
前記ブロック層の上に第1の導電材料を堆積させるステップと、
前記第1の側と反対側を向いている、前記基板の第2の側に貫通ビアを作るステップと、
前記貫通ビアに第2の導電材料を堆積させて、前記開口部を貫通する前記第1の導電材料に接触させるステップと
を含む、集積回路を製造する方法。 - 前記第2の導電材料を堆積させる前に、前記貫通ビアに絶縁層を堆積させるステップをさらに含む、請求項14に記載の方法。
- 前記ブロック層のパターンを作るステップが、前記貫通ビアの位置に対応する前記開口部のパターンを作るステップを含む、請求項14に記載の方法。
- 前記ブロック層のパターンを作るステップが、窒化ケイ素および炭化ケイ素の少なくとも一方のパターンを作るステップを含む、請求項14に記載の方法。
- 前記集積回路を、モバイルフォン、セットトップボックス、音楽プレーヤ、ビデオプレーヤ、エンターテインメントユニット、ナビゲーションデバイス、コンピュータ、ハンドヘルドパーソナル通信システム(PCS)ユニット、ポータブルデータユニット、および、固定ロケーションデータユニットのうちの少なくとも1つに組み込むステップをさらに含む、請求項14に記載の方法。
- 基板と、
前記基板の第1の側における、開口部を有する金属線の短絡を防止するための手段と、
前記基板を貫通して延びている、前記基板の第2の側における貫通ビアと、
前記開口部の中に延びている、前記防止手段の上の第1の導電層と、
前記第1の導電層と結合している、前記貫通ビアの上の第2の導電層と
を含む、集積回路。 - モバイルフォン、セットトップボックス、音楽プレーヤ、ビデオプレーヤ、エンターテインメントユニット、ナビゲーションデバイス、コンピュータ、ハンドヘルドパーソナル通信システム(PCS)ユニット、ポータブルデータユニット、および、固定ロケーションデータユニットのうちの少なくとも1つに組み込まれている、請求項19に記載の集積回路。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/757,570 | 2010-04-09 | ||
US12/757,570 US20110248405A1 (en) | 2010-04-09 | 2010-04-09 | Selective Patterning for Low Cost through Vias |
PCT/US2011/031230 WO2011127041A1 (en) | 2010-04-09 | 2011-04-05 | Selective patterning for low cost through vias |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2015002241A Division JP2015073134A (ja) | 2010-04-09 | 2015-01-08 | 低コストの貫通ビアのための選択的パターニング |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2013524534A true JP2013524534A (ja) | 2013-06-17 |
Family
ID=43927624
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013503836A Pending JP2013524534A (ja) | 2010-04-09 | 2011-04-05 | 低コストの貫通ビアのための選択的パターニング |
JP2015002241A Pending JP2015073134A (ja) | 2010-04-09 | 2015-01-08 | 低コストの貫通ビアのための選択的パターニング |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2015002241A Pending JP2015073134A (ja) | 2010-04-09 | 2015-01-08 | 低コストの貫通ビアのための選択的パターニング |
Country Status (6)
Country | Link |
---|---|
US (1) | US20110248405A1 (ja) |
EP (1) | EP2556730A1 (ja) |
JP (2) | JP2013524534A (ja) |
KR (2) | KR20130014568A (ja) |
CN (1) | CN102884870A (ja) |
WO (1) | WO2011127041A1 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2017209296A1 (ja) * | 2016-06-03 | 2017-12-07 | 大日本印刷株式会社 | 貫通電極基板及びその製造方法、並びに実装基板 |
WO2023080375A1 (ko) * | 2021-11-02 | 2023-05-11 | 울산과학기술원 | 고온공정을 포함한 mems 제작공정에 적합한 실리콘 관통 전극 및 이의 제조방법 |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130207745A1 (en) * | 2012-02-13 | 2013-08-15 | Qualcomm Incorporated | 3d rf l-c filters using through glass vias |
US8803648B2 (en) | 2012-05-03 | 2014-08-12 | Qualcomm Mems Technologies, Inc. | Three-dimensional multilayer solenoid transformer |
US20140023430A1 (en) * | 2012-07-19 | 2014-01-23 | Apple Inc. | Attachment Techniques |
US10115671B2 (en) | 2012-08-03 | 2018-10-30 | Snaptrack, Inc. | Incorporation of passives and fine pitch through via for package on package |
US9203373B2 (en) | 2013-01-11 | 2015-12-01 | Qualcomm Incorporated | Diplexer design using through glass via technology |
US20140247269A1 (en) * | 2013-03-04 | 2014-09-04 | Qualcomm Mems Technologies, Inc. | High density, low loss 3-d through-glass inductor with magnetic core |
US9012912B2 (en) * | 2013-03-13 | 2015-04-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafers, panels, semiconductor devices, and glass treatment methods |
US9935166B2 (en) | 2013-03-15 | 2018-04-03 | Qualcomm Incorporated | Capacitor with a dielectric between a via and a plate of the capacitor |
US9634640B2 (en) | 2013-05-06 | 2017-04-25 | Qualcomm Incorporated | Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) and related components and methods |
US9264013B2 (en) | 2013-06-04 | 2016-02-16 | Qualcomm Incorporated | Systems for reducing magnetic coupling in integrated circuits (ICS), and related components and methods |
US9296646B2 (en) | 2013-08-29 | 2016-03-29 | Corning Incorporated | Methods for forming vias in glass substrates |
US9342727B2 (en) | 2014-03-04 | 2016-05-17 | Apple Inc. | Field shaping channels in a substrate above a biometric sensing device |
US10410883B2 (en) | 2016-06-01 | 2019-09-10 | Corning Incorporated | Articles and methods of forming vias in substrates |
US10794679B2 (en) | 2016-06-29 | 2020-10-06 | Corning Incorporated | Method and system for measuring geometric parameters of through holes |
US10134657B2 (en) | 2016-06-29 | 2018-11-20 | Corning Incorporated | Inorganic wafer having through-holes attached to semiconductor wafer |
US11078112B2 (en) | 2017-05-25 | 2021-08-03 | Corning Incorporated | Silica-containing substrates with vias having an axially variable sidewall taper and methods for forming the same |
US10580725B2 (en) | 2017-05-25 | 2020-03-03 | Corning Incorporated | Articles having vias with geometry attributes and methods for fabricating the same |
US11554984B2 (en) | 2018-02-22 | 2023-01-17 | Corning Incorporated | Alkali-free borosilicate glasses with low post-HF etch roughness |
JP2019145737A (ja) * | 2018-02-23 | 2019-08-29 | ソニーセミコンダクタソリューションズ株式会社 | 半導体装置および半導体装置の製造方法 |
CN112912995A (zh) * | 2018-10-19 | 2021-06-04 | 康宁股份有限公司 | 包括通孔的装置及用于制造通孔的方法和材料 |
CN109860143B (zh) * | 2019-02-27 | 2022-01-14 | 京东方科技集团股份有限公司 | 阵列基板、显示装置及制备方法、拼接显示装置 |
US20220148973A1 (en) | 2019-04-15 | 2022-05-12 | Dai Nippon Printing Co., Ltd. | Through electrode substrate, electronic unit, method for manufacturing through electrode substrate, and method for manufacturing electronic unit |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63126250A (ja) * | 1986-11-15 | 1988-05-30 | Mitsubishi Electric Corp | 半導体装置、およびその製造方法 |
JP2002280490A (ja) * | 2001-03-21 | 2002-09-27 | Fujitsu Ltd | 配線基板とその製造方法並びにそれを用いた半導体装置 |
JP2008210952A (ja) * | 2007-02-26 | 2008-09-11 | Sanyo Electric Co Ltd | 半導体装置の製造方法、シリコンインターポーザの製造方法および半導体モジュールの製造方法 |
JP2009021433A (ja) * | 2007-07-12 | 2009-01-29 | Fujikura Ltd | 配線基板及びその製造方法 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3761782A (en) * | 1971-05-19 | 1973-09-25 | Signetics Corp | Semiconductor structure, assembly and method |
JP3401404B2 (ja) * | 1997-05-28 | 2003-04-28 | 早川ゴム株式会社 | 管の接続構造 |
US7205635B1 (en) * | 1998-03-20 | 2007-04-17 | Mcsp, Llc | Hermetic wafer scale integrated circuit structure |
US6355950B1 (en) * | 1998-09-23 | 2002-03-12 | Intel Corporation | Substrate interconnect for power distribution on integrated circuits |
JP2002317893A (ja) * | 2001-04-20 | 2002-10-31 | Nishikawa Rubber Co Ltd | 可撓性枝管継手 |
KR100691725B1 (ko) * | 2002-12-11 | 2007-03-12 | 다이니폰 인사츠 가부시키가이샤 | 다층 배선기판 및 그 제조 방법 |
US6841883B1 (en) * | 2003-03-31 | 2005-01-11 | Micron Technology, Inc. | Multi-dice chip scale semiconductor components and wafer level methods of fabrication |
TWI234261B (en) * | 2004-09-10 | 2005-06-11 | Touch Micro System Tech | Method of forming wafer backside interconnects |
US20080191297A1 (en) * | 2007-02-12 | 2008-08-14 | Advanced Chip Engineering Technology Inc. | Wafer level image sensor package with die receiving cavity and method of the same |
CN101599476A (zh) * | 2008-06-04 | 2009-12-09 | 台湾应解股份有限公司 | 薄型双面封装基板及其制造方法 |
JP4368941B1 (ja) * | 2009-05-20 | 2009-11-18 | 有限会社 渡辺鉄鋼建設 | バンドの巻回通路形成工事用工具およびバンドの巻回通路形成工事方法 |
-
2010
- 2010-04-09 US US12/757,570 patent/US20110248405A1/en not_active Abandoned
-
2011
- 2011-04-05 EP EP11713973A patent/EP2556730A1/en not_active Withdrawn
- 2011-04-05 CN CN2011800232681A patent/CN102884870A/zh active Pending
- 2011-04-05 KR KR1020127029365A patent/KR20130014568A/ko active Application Filing
- 2011-04-05 JP JP2013503836A patent/JP2013524534A/ja active Pending
- 2011-04-05 KR KR20147035635A patent/KR20150010000A/ko not_active Application Discontinuation
- 2011-04-05 WO PCT/US2011/031230 patent/WO2011127041A1/en active Application Filing
-
2015
- 2015-01-08 JP JP2015002241A patent/JP2015073134A/ja active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63126250A (ja) * | 1986-11-15 | 1988-05-30 | Mitsubishi Electric Corp | 半導体装置、およびその製造方法 |
JP2002280490A (ja) * | 2001-03-21 | 2002-09-27 | Fujitsu Ltd | 配線基板とその製造方法並びにそれを用いた半導体装置 |
JP2008210952A (ja) * | 2007-02-26 | 2008-09-11 | Sanyo Electric Co Ltd | 半導体装置の製造方法、シリコンインターポーザの製造方法および半導体モジュールの製造方法 |
JP2009021433A (ja) * | 2007-07-12 | 2009-01-29 | Fujikura Ltd | 配線基板及びその製造方法 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2017209296A1 (ja) * | 2016-06-03 | 2017-12-07 | 大日本印刷株式会社 | 貫通電極基板及びその製造方法、並びに実装基板 |
JP6323768B1 (ja) * | 2016-06-03 | 2018-05-16 | 大日本印刷株式会社 | 貫通電極基板及びその製造方法、並びに実装基板 |
WO2023080375A1 (ko) * | 2021-11-02 | 2023-05-11 | 울산과학기술원 | 고온공정을 포함한 mems 제작공정에 적합한 실리콘 관통 전극 및 이의 제조방법 |
Also Published As
Publication number | Publication date |
---|---|
KR20150010000A (ko) | 2015-01-27 |
JP2015073134A (ja) | 2015-04-16 |
EP2556730A1 (en) | 2013-02-13 |
CN102884870A (zh) | 2013-01-16 |
KR20130014568A (ko) | 2013-02-07 |
US20110248405A1 (en) | 2011-10-13 |
WO2011127041A1 (en) | 2011-10-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2015073134A (ja) | 低コストの貫通ビアのための選択的パターニング | |
KR101733608B1 (ko) | 패키지 기판에 매립된 박막 캐패시터의 집적 | |
JP5859514B2 (ja) | 積層集積回路のための二面の相互接続されたcmos | |
JP5969533B2 (ja) | 磁気トンネル接合デバイスおよび製作 | |
US8492874B2 (en) | High density metal-insulator-metal trench capacitor | |
JP2016004833A (ja) | 配線基板及びその製造方法 | |
TW201732883A (zh) | 用於後段製程線路(beol)互連之柵格自行對準金屬穿孔處理方法及由其所生成的結構 | |
US20110012239A1 (en) | Barrier Layer On Polymer Passivation For Integrated Circuit Packaging | |
JP6113130B2 (ja) | フィーチャのめっきのための選択的なシード層の処理 | |
JP6186780B2 (ja) | 半導体装置およびその製造方法 | |
KR20190042570A (ko) | 니켈-주석 마이크로범프 구조체 및 이의 제조 방법 | |
JP2016514909A (ja) | 酸化層を備える低コストインターポーザ | |
TW201236091A (en) | Conductive sidewall for microbumps | |
US9231046B2 (en) | Capacitor using barrier layer metallurgy | |
CN107004636B (zh) | 通孔材料选择和处理 | |
KR102515383B1 (ko) | 일체형의 부착 구조체를 가진 매립형 트레이스를 구비한 마이크로 전자 기판 | |
US9818817B2 (en) | Metal-insulator-metal capacitor over conductive layer | |
TWI694574B (zh) | 電子封裝體及形成電氣封裝體之方法 | |
JP5880508B2 (ja) | 配線基板およびその製造方法 | |
KR100688719B1 (ko) | 반도체 금속 배선 형성 방법 | |
JP2010016031A (ja) | 半導体記憶装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20130912 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130917 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20131217 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20140210 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20140508 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20140515 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20140610 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20140617 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140805 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20140908 |