JP2013516063A - ウエハプロセシング中に半導体ウエハに与えられる汚染物混入の量をモニタリングするための方法 - Google Patents

ウエハプロセシング中に半導体ウエハに与えられる汚染物混入の量をモニタリングするための方法 Download PDF

Info

Publication number
JP2013516063A
JP2013516063A JP2012545505A JP2012545505A JP2013516063A JP 2013516063 A JP2013516063 A JP 2013516063A JP 2012545505 A JP2012545505 A JP 2012545505A JP 2012545505 A JP2012545505 A JP 2012545505A JP 2013516063 A JP2013516063 A JP 2013516063A
Authority
JP
Japan
Prior art keywords
silicon
less
metal
insulator structure
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2012545505A
Other languages
English (en)
Japanese (ja)
Other versions
JP2013516063A5 (https=
Inventor
ジェフリー・エル・リバート
ル・フェイ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SunEdison Inc
Original Assignee
MEMC Electronic Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MEMC Electronic Materials Inc filed Critical MEMC Electronic Materials Inc
Publication of JP2013516063A publication Critical patent/JP2013516063A/ja
Publication of JP2013516063A5 publication Critical patent/JP2013516063A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/20—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by the properties tested or measured, e.g. structural or electrical properties
    • H10P74/203—Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/06—Apparatus for monitoring, sorting, marking, testing or measuring
    • H10P72/0604—Process monitoring, e.g. flow or thickness monitoring
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/23—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes
    • H10P74/235—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes comprising optical enhancement of defects or not-directly-visible states

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
JP2012545505A 2009-12-23 2010-12-17 ウエハプロセシング中に半導体ウエハに与えられる汚染物混入の量をモニタリングするための方法 Pending JP2013516063A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US28987809P 2009-12-23 2009-12-23
US61/289,878 2009-12-23
PCT/IB2010/055925 WO2011077344A2 (en) 2009-12-23 2010-12-17 Method for monitoring the amount of contamination imparted into semiconductor wafers during wafer processing

Publications (2)

Publication Number Publication Date
JP2013516063A true JP2013516063A (ja) 2013-05-09
JP2013516063A5 JP2013516063A5 (https=) 2013-07-25

Family

ID=43797704

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012545505A Pending JP2013516063A (ja) 2009-12-23 2010-12-17 ウエハプロセシング中に半導体ウエハに与えられる汚染物混入の量をモニタリングするための方法

Country Status (8)

Country Link
US (4) US8143078B2 (https=)
EP (1) EP2517234A2 (https=)
JP (1) JP2013516063A (https=)
KR (1) KR101762463B1 (https=)
CN (1) CN102687260A (https=)
SG (1) SG181427A1 (https=)
TW (1) TWI528482B (https=)
WO (1) WO2011077344A2 (https=)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014036122A (ja) * 2012-08-09 2014-02-24 Sumco Corp エピタキシャル成長炉の評価方法およびエピタキシャルウェーハの製造方法
JP2016063213A (ja) * 2014-09-18 2016-04-25 株式会社Sumco エピタキシャルシリコンウェーハ
KR20200037071A (ko) * 2018-09-28 2020-04-08 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 컨택 예비 세정
JP2022534633A (ja) * 2018-09-07 2022-08-03 メムススター リミテッド 薄膜層の欠陥検出方法

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5407473B2 (ja) * 2009-03-25 2014-02-05 株式会社Ｓｕｍｃｏ シリコンウェーハの製造方法
US9343379B2 (en) * 2011-10-14 2016-05-17 Sunedison Semiconductor Limited Method to delineate crystal related defects
US8835309B2 (en) * 2012-09-13 2014-09-16 International Business Machines Corporation Forming nickel—platinum alloy self-aligned silicide contacts
CN104078378A (zh) * 2014-07-02 2014-10-01 武汉新芯集成电路制造有限公司 一种检测金属污染的方法
TWI559424B (zh) * 2015-03-05 2016-11-21 力晶科技股份有限公司 半導體晶圓的金屬汙染即時監控方法
CN104713588B (zh) * 2015-03-20 2017-03-29 上海华力微电子有限公司 一种监控电子显微镜真空腔体洁净度的方法
CN106206334B (zh) * 2015-05-07 2019-01-22 中芯国际集成电路制造(上海)有限公司 监测晶圆以及金属污染的监测方法
CN107301960A (zh) * 2016-04-15 2017-10-27 上海新昇半导体科技有限公司 晶圆金属污染的评估方法
WO2018198797A1 (ja) * 2017-04-25 2018-11-01 株式会社Sumco シリコン単結晶の製造方法、エピタキシャルシリコンウェーハの製造方法、シリコン単結晶、および、エピタキシャルシリコンウェーハ
US10504805B2 (en) * 2017-08-24 2019-12-10 Applied Materials Israel Ltd. Method of examining defects in a semiconductor specimen and system thereof
CN111106024B (zh) * 2018-10-26 2023-09-29 长鑫存储技术有限公司 流场分布的检测方法
US11211272B2 (en) * 2019-09-25 2021-12-28 Micron Technology, Inc. Contaminant detection tools and related methods
CN111344852B (zh) * 2020-02-10 2021-08-31 长江存储科技有限责任公司 金属污染测试装置和方法
US12278124B2 (en) * 2021-10-28 2025-04-15 Applied Materials, Inc. Model-based controlled load lock pumping scheme
CN115793416B (zh) * 2023-01-16 2023-04-25 广州粤芯半导体技术有限公司 半导体器件制备方法及监测光刻工艺化学品杂质的方法
US12467877B2 (en) 2023-01-31 2025-11-11 Globalwafers Co., Ltd. Methods for detecting defects in a single crystal silicon structure
CN116387174B (zh) * 2023-03-27 2024-11-22 马鞍山芯乔科技有限公司 一种晶圆传递夹具污染自检测装置及其检测工艺

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH113923A (ja) * 1997-04-03 1999-01-06 Applied Materials Inc 半導体のサブミクロンシリコン表面層の金属汚染物質の検出方法
JPH1130611A (ja) * 1997-07-10 1999-02-02 Komatsu Electron Metals Co Ltd 水素中熱処理シリコンウェーハ及び熱処理用ボート、チューブの評価方法
JPH1174493A (ja) * 1997-08-29 1999-03-16 Sumitomo Metal Ind Ltd Ｓｏｉウエーハの欠陥検査方法
JPH11135584A (ja) * 1997-10-31 1999-05-21 Shin Etsu Handotai Co Ltd 金属不純物析出履歴の評価方法
JP2000164476A (ja) * 1998-11-26 2000-06-16 Mitsubishi Electric Corp 半導体製造工程の管理方法、半導体製造装置の管理方法、及び半導体製造環境の管理方法
JP2000193597A (ja) * 1998-12-24 2000-07-14 Sumitomo Metal Ind Ltd シリコンウェーハ表面の検査方法
JP2002110688A (ja) * 2000-09-29 2002-04-12 Canon Inc Ｓｏｉの熱処理方法及び製造方法
JP2003347374A (ja) * 2002-05-27 2003-12-05 Sumitomo Mitsubishi Silicon Corp Ｓｏｉ基板のｈｆ欠陥評価方法
US20040241867A1 (en) * 2003-01-17 2004-12-02 Jones Mark L. Method of analyzing a wafer for metal impurities

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2617798B2 (ja) * 1989-09-22 1997-06-04 三菱電機株式会社 積層型半導体装置およびその製造方法
JPH07106512A (ja) * 1993-10-04 1995-04-21 Sharp Corp 分子イオン注入を用いたｓｉｍｏｘ処理方法
JP3544280B2 (ja) * 1997-03-27 2004-07-21 株式会社半導体エネルギー研究所 半導体装置の作製方法
US6033974A (en) * 1997-05-12 2000-03-07 Silicon Genesis Corporation Method for controlled cleaving process
JP2000040723A (ja) 1998-07-23 2000-02-08 Shin Etsu Handotai Co Ltd 金属不純物検査用ウエーハ及び該ウエーハを用いた金属不純物検査方法
US6284384B1 (en) * 1998-12-09 2001-09-04 Memc Electronic Materials, Inc. Epitaxial silicon wafer with intrinsic gettering
JP2001050874A (ja) * 1999-08-04 2001-02-23 Mitsubishi Electric Corp 半導体基板の検査方法
US6528335B2 (en) * 2001-02-14 2003-03-04 International Business Machines Corporation Electrical method for assessing yield-limiting asperities in silicon-on-insulator wafers
JP2003288112A (ja) * 2002-03-28 2003-10-10 Matsushita Electric Ind Co Ltd 生産管理方法
US6825050B2 (en) * 2002-06-07 2004-11-30 Lam Research Corporation Integrated stepwise statistical process control in a plasma processing system
EP1369682A3 (en) 2002-06-07 2004-12-01 Interuniversitair Microelektronica Centrum Vzw A method for wafer level detection of integrity of a layer
US7016028B2 (en) * 2002-06-07 2006-03-21 Interuniversitair Microelektronica Centrum (Imec) Method and apparatus for defect detection
US7570353B2 (en) * 2005-12-16 2009-08-04 Infineon Technologies Ag Fabrication and test methods and systems
US7517706B2 (en) * 2006-07-21 2009-04-14 Sumco Corporation Method for evaluating quality of semiconductor substrate and method for manufacturing semiconductor substrate

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH113923A (ja) * 1997-04-03 1999-01-06 Applied Materials Inc 半導体のサブミクロンシリコン表面層の金属汚染物質の検出方法
JPH1130611A (ja) * 1997-07-10 1999-02-02 Komatsu Electron Metals Co Ltd 水素中熱処理シリコンウェーハ及び熱処理用ボート、チューブの評価方法
JPH1174493A (ja) * 1997-08-29 1999-03-16 Sumitomo Metal Ind Ltd Ｓｏｉウエーハの欠陥検査方法
JPH11135584A (ja) * 1997-10-31 1999-05-21 Shin Etsu Handotai Co Ltd 金属不純物析出履歴の評価方法
JP2000164476A (ja) * 1998-11-26 2000-06-16 Mitsubishi Electric Corp 半導体製造工程の管理方法、半導体製造装置の管理方法、及び半導体製造環境の管理方法
JP2000193597A (ja) * 1998-12-24 2000-07-14 Sumitomo Metal Ind Ltd シリコンウェーハ表面の検査方法
JP2002110688A (ja) * 2000-09-29 2002-04-12 Canon Inc Ｓｏｉの熱処理方法及び製造方法
JP2003347374A (ja) * 2002-05-27 2003-12-05 Sumitomo Mitsubishi Silicon Corp Ｓｏｉ基板のｈｆ欠陥評価方法
US20040241867A1 (en) * 2003-01-17 2004-12-02 Jones Mark L. Method of analyzing a wafer for metal impurities

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014036122A (ja) * 2012-08-09 2014-02-24 Sumco Corp エピタキシャル成長炉の評価方法およびエピタキシャルウェーハの製造方法
JP2016063213A (ja) * 2014-09-18 2016-04-25 株式会社Sumco エピタキシャルシリコンウェーハ
US9670581B2 (en) 2014-09-18 2017-06-06 Sumco Corporation Production method of epitaxial silicon wafer and vapor deposition apparatus
JP2022534633A (ja) * 2018-09-07 2022-08-03 メムススター リミテッド 薄膜層の欠陥検出方法
JP7442839B2 (ja) 2018-09-07 2024-03-05 メムススター リミテッド 薄膜層の欠陥検出方法
KR20200037071A (ko) * 2018-09-28 2020-04-08 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 컨택 예비 세정
KR102152760B1 (ko) 2018-09-28 2020-09-08 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 컨택 예비 세정

Also Published As

Publication number Publication date
WO2011077344A2 (en) 2011-06-30
US20110212550A1 (en) 2011-09-01
TW201142969A (en) 2011-12-01
US20120115258A1 (en) 2012-05-10
KR20120099733A (ko) 2012-09-11
TWI528482B (zh) 2016-04-01
KR101762463B1 (ko) 2017-07-27
WO2011077344A3 (en) 2011-10-13
SG181427A1 (en) 2012-07-30
US8143078B2 (en) 2012-03-27
US20110212547A1 (en) 2011-09-01
US8822242B2 (en) 2014-09-02
EP2517234A2 (en) 2012-10-31
CN102687260A (zh) 2012-09-19
US20110151592A1 (en) 2011-06-23

Similar Documents

Publication Publication Date Title
JP2013516063A (ja) ウエハプロセシング中に半導体ウエハに与えられる汚染物混入の量をモニタリングするための方法
US8796116B2 (en) Methods for reducing the metal content in the device layer of SOI structures and SOI structures produced by such methods
CN1932496B (zh) 硅晶片表面缺陷的评价方法
JP2014508405A5 (https=)
JP2013516063A5 (https=)
WO2004035879A1 (ja) シリコン単結晶インゴットの点欠陥分布を測定する方法
JP2007227516A (ja) シリコンウェーハ中のＣｕ評価方法
JP3896919B2 (ja) シリコンウエーハのＮｉ汚染の評価方法
JP7661510B2 (ja) 半導体基板の応力ロバストネスを試験するための方法
JP5042445B2 (ja) シリコンウェーハのゲッタリング効率を評価する方法
KR20030030634A (ko) 웨이퍼 표면 결함 분석 방법
JP2005228848A (ja) Ｓｉｍｏｘウェーハの検査方法及びそのｓｉｍｏｘウェーハの製造方法
JP3917245B2 (ja) シリコンウェーハ及び熱処理用ボート、チューブの評価方法
JP2007180485A (ja) 半導体基板の品質評価方法、半導体基板の製造方法
KR100501110B1 (ko) 실리콘웨이퍼의 표면 근방 결함 분석 방법
KR100901925B1 (ko) 웨이퍼의 게터링 평가 방법
CN120971120A (zh) 一种通过调控近表面铜浓度来表征近完美直拉硅片微缺陷的方法
KR20100101905A (ko) 웨이퍼 표면처리 공정이 개선된 ｄｓｏｄ 분석방법
KR20070090627A (ko) 웨이퍼의 결함 분석 방법

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130606

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20130606

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20140120

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20140128

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20140701