JP2013511153A5 - - Google Patents

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Publication number
JP2013511153A5
JP2013511153A5 JP2012538886A JP2012538886A JP2013511153A5 JP 2013511153 A5 JP2013511153 A5 JP 2013511153A5 JP 2012538886 A JP2012538886 A JP 2012538886A JP 2012538886 A JP2012538886 A JP 2012538886A JP 2013511153 A5 JP2013511153 A5 JP 2013511153A5
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JP
Japan
Prior art keywords
pattern
forming
tip
layer
photoresist features
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JP2012538886A
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English (en)
Japanese (ja)
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JP2013511153A (ja
JP5493009B2 (ja
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Priority claimed from US12/617,429 external-priority patent/US8304172B2/en
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Publication of JP2013511153A publication Critical patent/JP2013511153A/ja
Publication of JP2013511153A5 publication Critical patent/JP2013511153A5/ja
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Publication of JP5493009B2 publication Critical patent/JP5493009B2/ja
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JP2012538886A 2009-11-12 2010-11-09 設計規則違反を低減するために多重露光及び遮断マスクの手法を用いる半導体デバイス製造 Active JP5493009B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/617,429 US8304172B2 (en) 2009-11-12 2009-11-12 Semiconductor device fabrication using a multiple exposure and block mask approach to reduce design rule violations
US12/617,429 2009-11-12
PCT/US2010/055977 WO2011059961A2 (en) 2009-11-12 2010-11-09 Semiconductor device fabrication using a multiple exposure and block mask approach to reduce design rule violations

Publications (3)

Publication Number Publication Date
JP2013511153A JP2013511153A (ja) 2013-03-28
JP2013511153A5 true JP2013511153A5 (enExample) 2013-12-19
JP5493009B2 JP5493009B2 (ja) 2014-05-14

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ID=43858116

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012538886A Active JP5493009B2 (ja) 2009-11-12 2010-11-09 設計規則違反を低減するために多重露光及び遮断マスクの手法を用いる半導体デバイス製造

Country Status (6)

Country Link
US (1) US8304172B2 (enExample)
EP (1) EP2499660B1 (enExample)
JP (1) JP5493009B2 (enExample)
KR (1) KR101551416B1 (enExample)
CN (1) CN102754186B (enExample)
WO (1) WO2011059961A2 (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8739095B2 (en) * 2010-03-08 2014-05-27 Cadence Design Systems, Inc. Method, system, and program product for interactive checking for double pattern lithography violations
KR101948222B1 (ko) 2012-06-15 2019-02-14 에스케이하이닉스 주식회사 홀 패터닝을 위한 마스크패턴 및 그를 이용한 반도체장치 제조 방법
US10283437B2 (en) * 2012-11-27 2019-05-07 Advanced Micro Devices, Inc. Metal density distribution for double pattern lithography
US9236300B2 (en) * 2012-11-30 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Contact plugs in SRAM cells and the method of forming the same
JP6437452B2 (ja) 2013-01-14 2018-12-12 インサイト・ホールディングス・コーポレイションＩｎｃｙｔｅ Ｈｏｌｄｉｎｇｓ Ｃｏｒｐｏｒａｔｉｏｎ Ｐｉｍキナーゼ阻害剤として有用な二環式芳香族カルボキサミド化合物
US8910090B2 (en) * 2013-02-27 2014-12-09 Globalfoundries Inc. Methods involving pattern matching to identify and resolve potential non-double-patterning-compliant patterns in double patterning applications
WO2015095394A1 (en) * 2013-12-17 2015-06-25 Texas Instruments Incorporated Elongated contacts using litho-freeze-litho-etch process
US9472653B2 (en) * 2014-11-26 2016-10-18 Samsung Electronics Co., Ltd. Method for fabricating semiconductor device
US10430544B2 (en) * 2016-09-02 2019-10-01 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-patterning graph reduction and checking flow method
US11764062B2 (en) * 2017-11-13 2023-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor structure
US12400871B2 (en) * 2020-02-20 2025-08-26 International Business Machines Corporation Metal lines with low via-to-via spacing
CN116819906B (zh) * 2023-08-25 2023-11-28 深圳国微福芯技术有限公司 设计规则检查方法、光学临近修正方法
CN117153677B (zh) * 2023-10-27 2024-03-01 合肥晶合集成电路股份有限公司 一种半导体结构的制造方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6204187B1 (en) * 1999-01-06 2001-03-20 Infineon Technologies North America, Corp. Contact and deep trench patterning
TW436933B (en) * 1999-12-30 2001-05-28 Taiwan Semiconductor Mfg Method for defining a pattern
JP2002182363A (ja) * 2000-12-12 2002-06-26 Matsushita Electric Ind Co Ltd マスク及びパターン形成方法
JP2004247606A (ja) * 2003-02-14 2004-09-02 Fujitsu Ltd フォトマスク、半導体装置及びその製造方法
JP2005259991A (ja) * 2004-03-11 2005-09-22 Sony Corp パターン形成方法
JP2006294942A (ja) * 2005-04-12 2006-10-26 Toshiba Corp 半導体装置およびその製造方法
KR100642886B1 (ko) * 2005-06-27 2006-11-03 주식회사 하이닉스반도체 반도체 소자의 미세패턴 형성방법
US20070231748A1 (en) 2006-03-29 2007-10-04 Swaminathan Sivakumar Patterning trenches in a photoresist layer with tight end-to-end separation
US20070231743A1 (en) 2006-03-31 2007-10-04 Richard Selinfreund Optical media device with minipulatable read capability
JP2008153373A (ja) * 2006-12-15 2008-07-03 Toshiba Corp 半導体装置の製造方法
US7759235B2 (en) * 2007-06-07 2010-07-20 Infineon Technologies Ag Semiconductor device manufacturing methods
KR20090050699A (ko) * 2007-11-16 2009-05-20 주식회사 동부하이텍 미세 패턴 제조 방법 및 반도체 소자의 제조 방법
KR100944348B1 (ko) * 2008-05-16 2010-03-02 주식회사 하이닉스반도체 반도체 소자의 형성 방법
JP5319247B2 (ja) * 2008-11-14 2013-10-16 株式会社東芝 半導体装置の製造方法

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