JP5493009B2 - 設計規則違反を低減するために多重露光及び遮断マスクの手法を用いる半導体デバイス製造 - Google Patents

設計規則違反を低減するために多重露光及び遮断マスクの手法を用いる半導体デバイス製造 Download PDF

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JP5493009B2
JP5493009B2 JP2012538886A JP2012538886A JP5493009B2 JP 5493009 B2 JP5493009 B2 JP 5493009B2 JP 2012538886 A JP2012538886 A JP 2012538886A JP 2012538886 A JP2012538886 A JP 2012538886A JP 5493009 B2 JP5493009 B2 JP 5493009B2
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pattern
tip
mask
layer
forming
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JP2013511153A (ja
JP2013511153A5 (enExample
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シュルツ リチャード
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H10P76/2041—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10P50/73—
    • H10P76/40—

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Semiconductor Memories (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Electron Beam Exposure (AREA)
JP2012538886A 2009-11-12 2010-11-09 設計規則違反を低減するために多重露光及び遮断マスクの手法を用いる半導体デバイス製造 Active JP5493009B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/617,429 2009-11-12
US12/617,429 US8304172B2 (en) 2009-11-12 2009-11-12 Semiconductor device fabrication using a multiple exposure and block mask approach to reduce design rule violations
PCT/US2010/055977 WO2011059961A2 (en) 2009-11-12 2010-11-09 Semiconductor device fabrication using a multiple exposure and block mask approach to reduce design rule violations

Publications (3)

Publication Number Publication Date
JP2013511153A JP2013511153A (ja) 2013-03-28
JP2013511153A5 JP2013511153A5 (enExample) 2013-12-19
JP5493009B2 true JP5493009B2 (ja) 2014-05-14

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JP2012538886A Active JP5493009B2 (ja) 2009-11-12 2010-11-09 設計規則違反を低減するために多重露光及び遮断マスクの手法を用いる半導体デバイス製造

Country Status (6)

Country Link
US (1) US8304172B2 (enExample)
EP (1) EP2499660B1 (enExample)
JP (1) JP5493009B2 (enExample)
KR (1) KR101551416B1 (enExample)
CN (1) CN102754186B (enExample)
WO (1) WO2011059961A2 (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8739095B2 (en) * 2010-03-08 2014-05-27 Cadence Design Systems, Inc. Method, system, and program product for interactive checking for double pattern lithography violations
KR101948222B1 (ko) * 2012-06-15 2019-02-14 에스케이하이닉스 주식회사 홀 패터닝을 위한 마스크패턴 및 그를 이용한 반도체장치 제조 방법
US10283437B2 (en) * 2012-11-27 2019-05-07 Advanced Micro Devices, Inc. Metal density distribution for double pattern lithography
US9236300B2 (en) * 2012-11-30 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Contact plugs in SRAM cells and the method of forming the same
EP2943485B1 (en) 2013-01-14 2017-09-20 Incyte Holdings Corporation Bicyclic aromatic carboxamide compounds useful as pim kinase inhibitors
US8910090B2 (en) 2013-02-27 2014-12-09 Globalfoundries Inc. Methods involving pattern matching to identify and resolve potential non-double-patterning-compliant patterns in double patterning applications
CN114093812A (zh) * 2013-12-17 2022-02-25 德克萨斯仪器股份有限公司 使用光刻-冷冻-光刻-蚀刻工艺的细长接触件
US9472653B2 (en) * 2014-11-26 2016-10-18 Samsung Electronics Co., Ltd. Method for fabricating semiconductor device
US10430544B2 (en) * 2016-09-02 2019-10-01 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-patterning graph reduction and checking flow method
US11764062B2 (en) * 2017-11-13 2023-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor structure
US12400871B2 (en) * 2020-02-20 2025-08-26 International Business Machines Corporation Metal lines with low via-to-via spacing
CN116819906B (zh) * 2023-08-25 2023-11-28 深圳国微福芯技术有限公司 设计规则检查方法、光学临近修正方法
CN117153677B (zh) * 2023-10-27 2024-03-01 合肥晶合集成电路股份有限公司 一种半导体结构的制造方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6204187B1 (en) * 1999-01-06 2001-03-20 Infineon Technologies North America, Corp. Contact and deep trench patterning
TW436933B (en) * 1999-12-30 2001-05-28 Taiwan Semiconductor Mfg Method for defining a pattern
JP2002182363A (ja) * 2000-12-12 2002-06-26 Matsushita Electric Ind Co Ltd マスク及びパターン形成方法
JP2004247606A (ja) * 2003-02-14 2004-09-02 Fujitsu Ltd フォトマスク、半導体装置及びその製造方法
JP2005259991A (ja) * 2004-03-11 2005-09-22 Sony Corp パターン形成方法
JP2006294942A (ja) * 2005-04-12 2006-10-26 Toshiba Corp 半導体装置およびその製造方法
KR100642886B1 (ko) * 2005-06-27 2006-11-03 주식회사 하이닉스반도체 반도체 소자의 미세패턴 형성방법
US20070231748A1 (en) * 2006-03-29 2007-10-04 Swaminathan Sivakumar Patterning trenches in a photoresist layer with tight end-to-end separation
US20070231743A1 (en) 2006-03-31 2007-10-04 Richard Selinfreund Optical media device with minipulatable read capability
JP2008153373A (ja) * 2006-12-15 2008-07-03 Toshiba Corp 半導体装置の製造方法
US7759235B2 (en) * 2007-06-07 2010-07-20 Infineon Technologies Ag Semiconductor device manufacturing methods
KR20090050699A (ko) * 2007-11-16 2009-05-20 주식회사 동부하이텍 미세 패턴 제조 방법 및 반도체 소자의 제조 방법
KR100944348B1 (ko) * 2008-05-16 2010-03-02 주식회사 하이닉스반도체 반도체 소자의 형성 방법
JP5319247B2 (ja) * 2008-11-14 2013-10-16 株式会社東芝 半導体装置の製造方法

Also Published As

Publication number Publication date
KR20120099428A (ko) 2012-09-10
EP2499660B1 (en) 2019-10-02
JP2013511153A (ja) 2013-03-28
CN102754186A (zh) 2012-10-24
WO2011059961A2 (en) 2011-05-19
US20110111348A1 (en) 2011-05-12
WO2011059961A3 (en) 2012-04-05
CN102754186B (zh) 2016-04-13
KR101551416B1 (ko) 2015-09-08
US8304172B2 (en) 2012-11-06
EP2499660A2 (en) 2012-09-19

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